Timing generator for semiconductor test system

Details Timing generator for semiconductor test system Timing generator for semiconductor test system

1999-04-09

2000-05-02

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Testing

365233, G11C 700

Patent

active

060580577

ABSTRACT:
A timing generator for a semiconductor test system having an interleave architecture with no interleave jitters. The timing generator includes a plurality of timing data generators arranged in a parallel fashion and provided with a first clock signal in which each of the timing data generator produces a coarse timing signal and a delay time data based on timing data provided by a test program, a multiplexer provided with a second clock signal having a frequency higher than the first clock signal for receiving the coarse timing signals and delay data in parallel and produces selected one of coarse timing signal and the delay data in series, and a variable delay circuit which receives the coarse timing signal and the delay data from the multiplexer for providing a delay time defined by the delay data to the coarse timing signal.

REFERENCES:
patent: 5291449 (1994-03-01), Dehara

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