Timing generator

Details Timing generator Timing generator

1999-04-05

2001-06-26

Nguyen, Tan T. (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06253360

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a timing generator which is suitable for use in a semiconductor device testing apparatus (commonly called IC tester) for testing a semiconductor device such as, for example, a semiconductor integrated circuit (IC), and more particularly, to an improvement in a clock data processing circuit used in the timing generator.
BACKGROUND ART
Heretofore, semiconductor integrated circuits (hereinafter referred to as IC) are classified mainly into two types one of which is called memory ICs in which a memory portion of each of memory ICs is dominant, and the other of which is called logic ICs in which a logic circuit portion (logic portion) of each of logic ICs is dominant. The memory ICs are trending towards an increase in the number of pins (the number of terminals) thereof according to the increased memory capacity in recent years.
Since the testing methods of memory ICs and logic ICs are markedly different from each other, an IC tester for testing memory ICs (a memory testing system) and an IC tester for testing logic ICs (a logic testing system) have been separately constructed, thereby to test memory ICs and logic ICs using those IC testers, respectively.
FIG. 4
is a block diagram showing a general construction of an example of the conventional IC tester for testing a memory IC (the conventional memory testing system). The illustrated IC tester TES comprises a main controller
11
, a pattern generator
12
, a timing generator
13
, a waveform shaping device
14
, a waveform generator
15
, a logical comparator
18
, a group of drivers
16
, a group of analog comparators
17
, a failure analysis memory
19
, and a device power supply PS.
The main controller
11
is generally constructed by a computer system, and mainly controls the pattern generator
12
and the timing generator
13
in accordance with a test program PM created by a user.
Before a testing for ICs is started, various kinds of data are set in the IC tester from the main controller
11
. For example, the main controller
11
transfers pattern information to the pattern generator
12
to store the information in a memory for pattern (not shown) provided in the pattern generator
12
. In addition, the main controller
11
first transfers period data to the timing generator
13
to store the data in a period data memory provided in a period generator (not shown) which is one of the components for constituting the timing generator
13
as well as in a period data memory provided in a clock data processing circuit (not shown) which is one of the components for constituting the timing generator
13
, respectively. Secondly, the main controller
11
transfers clock data to the clock data processing circuit to read out a period data previously set in the period data memory of the clock data processing circuit therefrom thereby performing an arithmetic and logic operation process between the read-out period data and the clock data, the result of the operation process or the transferred clock data being stored in a clock data memory provided in a clock generator (not shown) which is also one of the components for constituting the timing generator
13
. The settings of the main data relating to the present invention have substantially completed with this.
In order to sequentially carry out such settings of the various kinds of data from the main controller
11
, it is necessary that the period data is set at least in the period data memory of the clock data processing circuit prior to setting of the clock data.
After the various kinds of data have been set, a testing for ICs is started. First, the main controller
11
issues a test start instruction or command to the pattern generator
12
. As a result, the pattern generator
12
starts to generate a patter. Accordingly, the time point that the pattern generator
12
starts to generate a pattern becomes the time point of starting a testing. The pattern generator
12
supplies test pattern data PTND to the waveform shaping device
14
and at the same time, supplies timing set information (which is also called timing set data) TS to the period generator and the clock generator of the timing generator
13
.
The timing set information means a pair of one information for selecting period data previously set in the period data memory of the period generator and another information for selecting clock data previously set in the clock data memory of the clock generator. As described later in detail, in the period data memory of the period generator are set time intervals of period data corresponding to the numbers of the timing set information (TS1, TS2, TS
3
1, . . . ), usually, in a unit of nanosecond (ns) (for example, TS1 is 90 ns, TS2 is 130 ns , TS3 is 80 ns,) . . . , and similarly, in the clock data memory of the clock generator are set time intervals of period data corresponding to the numbers of the timing set information in a unit of nanosecond (ns) (for example, TS1 is 100 ns, TS2 is 80 ns, TS3 is 30 ns, . . . ). Accordingly, the timing set information means, in this example, information for indicating the number of the timing set information for each of pattern generating cycles such that the first cycle of the pattern generating cycles is TS1, the second cycle of the pattern generating cycles is TS4, the third cycle of the pattern generating cycles is TS2, the fourth cycle of the pattern generating cycles is TS5, . . . . The timing set information is previously programmed by a user.
By application of the timing set information TS to the timing generator
13
, the timing generator
13
generates a timing signal (clock pulse) for controlling timings of operation of the waveform shaping device
14
, the logical comparator
19
and the like.
The test pattern data PTND is converted to a test pattern signal having a real waveform by the waveform shaping device
14
and the waveform generator
15
located at the succeeding stage of the waveform shaping device
14
. The waveform shaping device
14
and the waveform generator
15
are to be described later in detail. The converted test pattern signal is applied to an IC under test (commonly called DUT)
20
through a group of the drivers
16
to store it in the memory of the IC under test
20
.
On the other hand, a response signal read out of the IC under test
20
is compared in a group of the analog comparators
17
with a reference voltage from a comparison reference voltage source (not shown) to determine whether or not the response signal has a predetermined logical level (a voltage of H logical level (high logical level), or a voltage of L logical level (low logical level)). A response signal which is determined to have the predetermined logical level is sent to the logical comparator
18
where the response signal is compared with an expected value data outputted from the pattern generator
12
. When the response signal does not coincide with the expected value data, the memory cell of the IC under test
20
at the address thereof from which the response signal is read out is determined to be defective or a failure, and the address of the failure memory cell is stored, each time a failure occurs, in the failure analysis memory
19
as a failure address. Usually, the address of a failure memory cell is stored in a memory cell of the failure analysis memory
19
having the same address as that of the IC under test
20
. At the time of completion of the test, the failure addresses stored in the failure analysis memory
19
are read out thereof to determine, for example, whether the failure memory cell or cells of the tested IC
20
can be relieved or not.
As discussed above, the timing generator
13
generates, in accordance with the timing set information TS given from the pattern generator
12
, a timing signal (clock pulse) for defining a rise timing and a fall timing of the waveform of a test pattern signal which is to be applied to an IC under test
20
, a timing signal (clock pulse) for a strobe pulse defining a timing of the logical comparison in the logical comparator
18

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