Timing failure analysis in a semiconductor device having a...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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C714S037000, C714S042000, C712S227000

Reexamination Certificate

active

07461295

ABSTRACT:
A method of testing a semiconductor device having a pipelined architecture. Operation of a first pipeline stage of the semiconductor is disabled during a first pipelined operation to establish test data at an input of a second pipeline stage of the semiconductor device. A second pipelined operation is executed to enable the second pipeline stage to generate an intermediate result using the test data. A final result of the second pipelined operation is evaluated to determine whether the second pipeline stage produced a correct intermediate result.

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Xiaogang Du; Reddy, S.M.; Rayhawk, J.; Wu-Tung Cheng, “Testing delay faults in embedded CAMs,” Test Symposium, 2003. ATS 2003. 12th Asian , vol., No., pp. 378-383, Nov. 16-19, 2003.

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