Timing error detector for digital signal receiver

Details Timing error detector for digital signal receiver Timing error detector for digital signal receiver

2006-01-10

2006-01-10

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Skew detection correction

Reexamination Certificate

active

06986080

ABSTRACT:
A received signal having a series of T-spaced symbols having more than two levels is sampled at a rate that produces successive samples SP, SC, and SNsubstantially equally spaced by T/2. An output representing the difference between the sign of the sample SNand the sign of the sample SPis generated, and the value of the sample SCis offset so that the value of the sample SCapproaches zero. The offset value of the sample SCand the generated output are multiplied together in order to provide a timing error signal. The sampling of the received signal is controlled in accordance with the timing error signal.

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patent: 6430235 (2002-08-01), O'Shea et al.
Gardner, “A BPSK/QPSK Timing-Error Detector for Sampled Receivers”, IEEE Transactions on Communication, vol. COM-34, No. 5, May 1986, pp. 423-429.
Litwin, “Matched Filtering and Timing Recovery in Digital Receivers”, Sep. 2001.
Gardner, “Interpolation in Digital Modems—Part 1: Fundamentals”, vol. 41, No. 3, Mar. 1993, IEEE Transactions on Communications.

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