Timing driven synthesis of sum-of-product functional blocks

Details Timing driven synthesis of sum-of-product functional blocks Timing driven synthesis of sum-of-product functional blocks

2006-03-22

2010-06-15

Mai, Tan V (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07739324

ABSTRACT:
In one embodiment of the invention, an integrated circuit (IC) design tool is provided that has a sum-of-products (SOP) synthesizer. The SOP synthesizer receives expected arrival times of signals including partial product terms of each bit-vector of a SOP functional block, a comparison gate delay, and a register-transfer-level (RTL) netlist in order to synthesize a gate-level netlist of the SOP functional block. The SOP synthesizer includes software modules to synthesize a partial products generator, a partial product reduction tree, and an adder. The synthesis of the partial product reduction tree is responsive to a comparison gate delay and the expected arrival times of the partial product terms in each bit vector.

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