Timing driven pin assignment

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07577933

ABSTRACT:
A mechanism is disclosed for determining pin assignments in an integrated circuit. More particularly, the mechanism involves accessing design information for the integrated circuit. The design information includes a floorplan that sets forth an arrangement of blocks in the integrated circuit and timing information for interconnections between the blocks. Based on the timing information, routing information is determined for the interconnections between the blocks. The routing information includes physical routes and physical pin placements for the interconnections.

REFERENCES:
patent: 4613941 (1986-09-01), Smith et al.
patent: 5737580 (1998-04-01), Hathaway et al.
patent: 5889677 (1999-03-01), Yasuda et al.
patent: 5889682 (1999-03-01), Omura et al.
patent: 6205570 (2001-03-01), Yamashita
patent: 6240541 (2001-05-01), Yasuda et al.
patent: 6286128 (2001-09-01), Pileggi et al.
patent: 6308302 (2001-10-01), Hathaway et al.
patent: 6415425 (2002-07-01), Chaudhary et al.
patent: 6467074 (2002-10-01), Katsioulas et al.
patent: 6505335 (2003-01-01), Tanaka
patent: 6507938 (2003-01-01), Roy-Neogi et al.
patent: 6557145 (2003-04-01), Boyle et al.
patent: 6629298 (2003-09-01), Camporese et al.
patent: 6691296 (2004-02-01), Nakayama et al.
patent: 6832328 (2004-12-01), Kishimoto
patent: 7155697 (2006-12-01), Teig et al.
patent: 7281233 (2007-10-01), Sivasubramaniam
patent: 7503026 (2009-03-01), Ichiryu et al.
patent: 2001/0010090 (2001-07-01), Boyle et al.
patent: 2002/0104063 (2002-08-01), Chang et al.
patent: 2002/0112220 (2002-08-01), Miller
patent: 2004/0111689 (2004-06-01), Kanaoka et al.
patent: 2004/0117753 (2004-06-01), Kahng et al.
patent: 2004/0172605 (2004-09-01), Kuge et al.
patent: 2004/0181766 (2004-09-01), Fukui et al.
patent: 2005/0097491 (2005-05-01), Katayose
patent: 2005/0114821 (2005-05-01), Petunin et al.
patent: 2005/0120316 (2005-06-01), Suaya et al.
patent: 2005/0172252 (2005-08-01), Cheng et al.
patent: 2006/0136848 (2006-06-01), Ichiryu et al.
patent: 2006/0168551 (2006-07-01), Mukuno
patent: 2006/0190899 (2006-08-01), Migatz et al.
patent: 2006/0294487 (2006-12-01), Bittner et al.
patent: 2007/0204253 (2007-08-01), Murakawa
patent: 2007/0220466 (2007-09-01), Davidovic
patent: 2008/0066039 (2008-03-01), Berry et al.
patent: 10056067 (1998-02-01), None
Meixner et al., “Timing Driven Pin Assignment in a Hierarchical Design Environment”, Euro ASIC '91, May 27-31, 1991, pp. 212-217.
Albrecht et al., “Floorplan Evaluation with Timing-Driven Global Wire Planning, Pin Assignment, and Buffer/Wire Sizing”, Proceedings of 7th Asia and South Pacific 15th International Conference on VLSI Design, Jan. 7-11, 2002, pp. 580-587.
Koide et al., “Pin Assignment with Global Routing for VLSI Building Block Layout”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, No. 12, Dec. 1996, pp. 1575-1583.
Harvatis et al., “Pin Assignment for High-Performance MCM Systems”, 1996 IEEE International Symposium on Circuits and Systems, vol. 4, May 12-15, 1996, pp. 771-774.
Her, “Pin Assignment with Timing Consideration [VLSI]”, 1996 IEEE International Symposium on Circuits and Systems, vol. 4, May 12-15, 1996, pp. 695-698.
Maidee et al., “Timing-Driven Partitioning-Based Placement for Island Style FPGAs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, No. 3, Mar. 2005, pp. 395-406.
Mandoiu, “Recent Advances in Multicommodity Flow Algorithms for Global Routing”, Proceedings of 5th International Conference on ASIC, vol. 1, Oct. 21-24, 2003, pp. 160-165.
Pedram et al., “Floorplanning with Pin Assignment”, 1990 IEEE International Conference on Computer-Aided Design, Nov. 11-15, 1990, pp. 98-101.
Wakabayashi et al., “Timing-Driven Pin Assignment with Improvement of Cell Placement in Standard Cell Layout”, Proceedings of 1997 IEEE International Symposium on Circuits and Systems, vol. 3, Jun. 9-12, 1997, pp. 1552-1555.
Synopsis Products: JupiterXT data sheet http://www.synopsys.com/products/jupiterxt/jupiterxt.html, 3 pages, printed on Feb. 9, 2007.
Synopsis Products: JupiterIO data sheet http://www.synopsys.com/products/jupiterIO/jupiterIO.html, 2 pages, printed on Feb. 9, 2007.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Timing driven pin assignment does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Timing driven pin assignment, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing driven pin assignment will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4091151

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.