Timing driven pin assignment

Details Timing driven pin assignment Timing driven pin assignment

2006-11-17

2009-08-18

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07577933

ABSTRACT:
A mechanism is disclosed for determining pin assignments in an integrated circuit. More particularly, the mechanism involves accessing design information for the integrated circuit. The design information includes a floorplan that sets forth an arrangement of blocks in the integrated circuit and timing information for interconnections between the blocks. Based on the timing information, routing information is determined for the interconnections between the blocks. The routing information includes physical routes and physical pin placements for the interconnections.

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Synopsis Products: JupiterIO data sheet http://www.synopsys.com/products/jupiterIO/jupiterIO.html, 2 pages, printed on Feb. 9, 2007.

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