Timing driven interconnect analysis

Details Timing driven interconnect analysis Timing driven interconnect analysis

2001-06-27

2003-03-11

Lam, Tuan T. (Department: 2816)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06532577

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to ASIC design methodologies, and more particularly to a timing driven method for performing interconnect estimation analysis used in front-end design processes, such as logic synthesis, floorplanning, and performance analysis.
BACKGROUND OF THE INVENTION
An application specific integrated circuit (ASIC) is a chip that is custom designed for a specific application, rather than a general-purpose chip such as a microprocessor. An ASIC chip performs an electronic operation as fast as it is possible to do so, providing, of course, that the circuit design is efficiently architected.
FIG. 1
is a block diagram illustrating a basic design flow for fabricating an ASIC. The design flow includes a front-end design process that creates a logical design for the ASIC, and a backend design process that creates a physical design for the ASIC. The front-end design process begins with providing a design entry
10
for an electronic circuit that is used to generate a high-level electronic circuit description, which is typically written in a Hardware Description Language (HDL)
12
. Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards.
The design includes a list of interconnections that need to be made between the cells of the circuit; but physical properties for the interconnects have yet to be determined. Therefore, the designer needs an estimation of physical properties to help determine a timing within circuit. Interconnect data from previous designs are used to generate interconnect statistical data to use as the estimation in step
14
. The interconnect statistical data is used to create a wire load model
16
, which defines the resistance, capacitance, and the area of all nets in the design. The statistically generated wire load model
16
is used to estimate the wire lengths in the design and define how net delays are computed.
The HDL
12
and the wire load model
16
are then input into a logic synthesis tool
18
to generate a list of logic gates and their interconnections, called a “netlist”
20
. It is important to use wire load models
16
when synthesizing a design, otherwise, timing information generated from synthesis will be optimistic in the absence of net delays. The timing information will also be inaccurate when a poor wire load model
16
is used.
Next, system partitioning is performed in step
22
in which the physical design is partitioned to define groupings of cells small enough to be timed accurately with wire load models
16
(local nets). The resulting design typically includes many cells with many interconnect paths, with many having large fanins and fanouts. A prelayout simulation is then performed in step
24
with successive refinement to the design entry
10
and to logic synthesis
18
to determine if the design functions properly.
After prelayout simulation
24
is satisfactory, the backend design process begins with floorplanning in step
26
in which the blocks of the netlist
20
are arranged on the chip. The location of the cells in the blocks are then determined during a placement process in step
28
. A routing process makes connections between cells and blocks in step
30
. Thereafter, circuit extraction determines the resistance and capacitance of the interconnects in step
32
. A postlayout simulation is then performed in step
34
with successive refinement to floorplanning
26
as necessary.
Although the physical knowledge of previous designs are incorporated early in the design flow, the design flow typically results in many post-layout design iterations to obtain timing closure between the finished physical design and the logical design. The post-layout timing iterations are due primarily to inaccurate wireload models
16
used at the front-end of the design cycle during logic synthesis
18
. Inaccurate wire load models
16
typically result from inaccurate analysis of the interconnect data of previous designs. The analysis of interconnect data for deep submicron designs may be even more inaccurate and may require even more iterative loops to obtain timing closure. The additional loops can add weeks or months to a project schedule and significantly increase the cost of the design.
Accordingly, what is needed is an improved method for analyzing interconnect data from previous designs for the generation of accurate wireload models during the ASIC design process. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method for performing timing driven interconnect estimation analysis. The method includes collecting data only from timing critical paths of at least one previous design, and generating statistical data based on a net length distribution of the timing critical paths. The method further includes generating a wire load model for a new design from the statistical data.
According to the system and method disclosed herein, the present invention provides a more accurate analysis of the interconnect data of previous designs, and therefore results in more accurate wireload models used for logic synthesis at the front-end of the design cycle. Consequently, the number post-layout timing iterations required to obtain timing closure will be minimized, thereby reducing the cost of the design.


REFERENCES:
patent: 5819072 (1998-10-01), Bushard et al.
patent: 6260185 (2001-07-01), Sasaki et al.
patent: 6286126 (2001-09-01), Raghavan et al.
patent: 6289498 (2001-09-01), Dupenloup
patent: 6327692 (2001-12-01), Brown
“Synthesis Methodology for Large Designs” Design Compiler 1997.01 Release, Jun. 1997, Don Chang, et al., http://www.synopsys.com/products/logic/dc_wp97.html.

Affiliated with

Also associated with

Rating

Timing driven interconnect analysis does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Timing driven interconnect analysis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing driven interconnect analysis will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3051035