Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Pulse multiplication or division
Patent
1988-10-19
1990-05-15
Miller, Stanley D.
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Pulse multiplication or division
377118, 307479, 307271, 307269, 328 15, 328 63, H03B 1900, H03K 2100
Patent
active
049264516
ABSTRACT:
There is disclosed a digital integrated circuit device which has high-speed transistors of a selected type. A timing controller is incorporated in this device and performs timing control for an internal digital circuit. The timing controller includes a series-circuit of two flip-flop circuits serving as a frequency-dividing circuit for frequency-dividing a reference clock signal and generating an internal timing signal, and a switch circuit connected to a signal feedback line of these flip-flop circuits. In a normal mode, the switch circuit supplies the internal timing signal output from the flip-flop circuits to the digital integrated circuit. At a desired timing, the switch circuit performs a switching operation in response to a control signal, electrically disconnects the signal feedback line of the flip-flop circuits, and alternatively supplies an external timing signal externally supplied thereto to the digital integrated circuit.
REFERENCES:
patent: 3896387 (1975-07-01), Kokado
patent: 4031476 (1977-07-01), Goldberg
patent: 4041403 (1977-08-01), Chiapparoli, Jr.
IEEE GaAs IC Symposium 1986; "High Yield and Low Power Multiplexer/Demultiplexer by SCFL"; Hasegawa et al. (pp. 147-150).
IEICE National Convention Record; "Design of Gbit/s Multiplexer and Demultiplexer IC's"; N. Koide et al.; Record No. 399, pp. 2-203; 1987.
(IEICE Technical Report); "A GaAs Multiplexer and Demultiplexer Chip-Set for Gbit/s Optical Fiber Transmission System"; A. Kameyama et al.; ED86-152 (1987).
Koide Nobuo
Shimizu Shoichi
Takubo Chiaki
Terada Toshiyuki
Yoshihara Kunio
Callahan Timothy P.
Kabushiki Kaisha Toshiba
Miller Stanley D.
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