Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2008-10-01
2011-11-29
Lefkowitz, Sumati (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
Reexamination Certificate
active
08068084
ABSTRACT:
A timing controller includes a receiver and a clock generator connected to output terminals of the receiver. The clock generator receives an external clock signal through the receiver and periodically modulates a frequency of the external clock signal to generate a modulation clock signal that is used to process a plurality of pixel data. The clock generator controls a delay time of the modulation clock signal based on a modulation rate of the frequency of the modulation clock signal. According to the timing controller, circuit blocks connected to output terminals of the clock generator are operated by the modulation clock signal. Thus, the circuit blocks operated by the delayed modulation clock signal may be prevented from malfunction due to electromagnetic interference.
REFERENCES:
patent: 6720943 (2004-04-01), Lee et al.
patent: 2006/0279506 (2006-12-01), Choi
patent: 2007/0229418 (2007-10-01), Yun et al.
patent: 2008/0252623 (2008-10-01), Yi
F. Chau & Associates LLC
Gillis Ieesha
Lefkowitz Sumati
Samsung Electronics Co,. Ltd.
LandOfFree
Timing controller, data processing method using the same and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Timing controller, data processing method using the same and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing controller, data processing method using the same and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4278236