Timing control of amplifiers in a memory

Details Timing control of amplifiers in a memory Timing control of amplifiers in a memory

1999-03-01

1999-11-02

Tran, Andrew Q.

Static information storage and retrieval

Read/write circuit

Signals

36523003, 365190, 365208, 365233, 365194, 365202, 3652257, 36518905, 36518902, G11C 706

Patent

active

059782862

ABSTRACT:
A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers that are coupled to the same global data lines are enabled by clocks that are timed by a common clock signal. The memory has subarrays in which each subarray is divided into blocks. When a block is selected, a corresponding block select signal is generated. The sense amplifiers and the secondary amplifiers that are coupled in common with the enabled sense amplifiers in the selected block are enabled in response to this block select signal. The block select signal that enables the sense amplifiers initiates a secondary amp control signal which, after a programmed delay, enables the secondary amplifier.

REFERENCES:
patent: 5485430 (1996-01-01), McClure
patent: 5550777 (1996-08-01), Tran

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