Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2008-03-04
2008-03-04
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Signals
C365S207000, C365S233100
Reexamination Certificate
active
11504766
ABSTRACT:
An integrated circuit18includes a memory20having timing circuitry formed of a global controller26and a self-timing path for triggering the sense amplifiers28to read bit lines30within the array of bit cells24. The self timing path includes timing cells34embedded within the array24and modelling behavior of the bit cells32in changing the bit line signals. The self timing path uses active low signalling throughout as this can be implemented with predominantly n-type transistors matching the n-type transistors which dominate within the array24.
REFERENCES:
patent: 3778784 (1973-12-01), Karp et al.
patent: 3906463 (1975-09-01), Yu
patent: 5625595 (1997-04-01), Ikeda
patent: 5627789 (1997-05-01), Kalb, Jr.
patent: 5852582 (1998-12-01), Cleveland et al.
patent: 6094379 (2000-07-01), Sago
patent: 6111796 (2000-08-01), Chang et al.
patent: 6249482 (2001-06-01), Albon et al.
patent: 6618309 (2003-09-01), DeMaris et al.
ARM Limited
Nguyen Tan T.
Nixon & Vanderhye P.C.
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