Timing control for sense amplifiers in a memory circuit

Details Timing control for sense amplifiers in a memory circuit Timing control for sense amplifiers in a memory circuit

2008-03-04

2008-03-04

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S207000, C365S233100

Reexamination Certificate

active

07339842

ABSTRACT:
An integrated circuit18includes a memory20having timing circuitry formed of a global controller26and a self-timing path for triggering the sense amplifiers28to read bit lines30within the array of bit cells24. The self timing path includes timing cells34embedded within the array24and modelling behavior of the bit cells32in changing the bit line signals. The self timing path uses active low signalling throughout as this can be implemented with predominantly n-type transistors matching the n-type transistors which dominate within the array24.

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