Timing control for a memory

Details Timing control for a memory Timing control for a memory

1990-10-11

1993-12-07

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Differential sensing

3652257, 365233, 437 52, G11C 700

Patent

active

052688690

ABSTRACT:
A memory circuit comprises a plurality of memory cells (2) arranged in rows and columns, the cells in each row being connected to a common wordline (4) and the cells in each column being connected between a pair of bit lines (6,8) across which a voltage differential is developed when a memory cell is accessed to be read; and a timing circuit (16) for producing a timing signal to control further circuitry in dependence on said voltage differential achieving a predetermined value. The memory circuit has a dummy bit line connected to a column of dummy cells, each dummy cell having the same structure as a memory cell. A plurality of said dummy cells (22) has a bit value stored therein and is connected to a dummy wordline and the remainder of said dummy cells are rendered inactive, whereby on addressing of the dummy wordline simultaneously with the wordline of an accessed cell, a predetermined number of dummy cells discharges via the dummy bit line so that the voltage developed on the dummy bit line bears a predetermined relationship to the voltage differential developed between the bit lines of the accessed cell. The timing circuit (16) is connected to receive the voltage differential on the dummy bit line (18).

REFERENCES:
patent: 4255679 (1981-03-01), White, Jr. et al.
patent: 4363111 (1982-12-01), Heightley et al.
patent: 4425633 (1984-01-01), Swain

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