Timing-control circuit device and clock distribution system

Details Timing-control circuit device and clock distribution system Timing-control circuit device and clock distribution system

1999-09-02

2001-10-09

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000, C327S161000, C327S298000

Reexamination Certificate

active

06300807

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, more particularly to a timing-control circuit and a clock distribution system which can generate and transmit or distribute a synchronous signal.
2. Description of the Related Art
Conventionally, a phase-locked loop (PLL) has been used for a semiconductor integrated circuit which handles a clock signal. The PLL circuit, as shown in
FIG. 45
, comprises a phase frequency detector
280
, a loop filter
281
, and a voltage controlled oscillator
282
. The PLL circuit detects a phase difference between the reference clock signal clkref
271
and the inner clock signal
277
entered to the phase frequency detector
280
and outputs a clock error signal clkerr
272
. The loop filter
281
rectifies the clock error signal clkerr
272
to a DC voltage and outputs the voltage as a control signal cntsig
273
. The voltage controlled oscillator
282
generates an output clock signal clkout
276
, which has a frequency determined by the voltage of the control signal cntsig
273
. The output clock signal cikout
276
is supplied to the phase frequency detector
280
as an inner clock signal cikin
277
. The phase frequency detector
280
stops the output if no difference is detected between input signals, thereby the PLL operation is stabilized. At this time, the reference clock signal clkref
271
and the output clock signal clkout
276
are synchronized with each other in phase. The PLL circuit takes a long time (several &mgr; sec) until the output clock signal clkout
276
generation is stabilized. Usually, when the subject system stands by, the PLL operation is stopped, thereby saving the power consumption.
However, the PLL circuit has a problem that the circuits needs a long settling time before it is restarted. In order to avoid such a long settling time, therefore, some systems are provided with a sleep mode respectively, which avoids stopping the PLL circuit even at the stand-by time. The PLL circuit thus consumes the power at its stand-by time.
The official gazette of Japanese Patent Laid-Open No.8-237091 has disclosed a synchronous mirror delay circuit for solving the disadvantages peculiar to such the PLL circuit. This synchronous mirror delay circuit does not multiply a frequency of any input clock signal. The circuit is dedicated just for phase synchronization. When compared with the PLL circuit, its power consumption is lower and its circuit size is smaller.
FIG. 44
shows a configuration of such a synchronous mirror delay circuit. The synchronous mirror delay circuit
260
comprises a forward delay array
261
, a backward delay array
263
, and a delay detect circuit
262
. The input clock signal cikin
251
, passing the replica of buffer
264
having a delay time of Tbuf2, becomes a delayed clock signal clkbuf
252
, then entered to the forward delay array
261
. The forward delay array
261
outputs a plurality of clock signals, each having a different delay time from the delayed clock signal clkbuf
252
. The clock signals are transmitted to the delay detect circuit
262
. Some of those signals from the forward delay array
261
have a delay time of (Tclk−Tbuf2). The delay detect circuit
262
detects the output positions of those (tclk−Tbuf2) signals using the input clock signal clkin
251
as a control signal. The Tclk indicates an cycle time of the input clock signal clkin
251
. The Tbuf2 indicates an operation delay time of the replica of buffer
264
. The delay detect circuit
262
transfers the detected signal to the backward delay array
263
. The clock signal is transmitted in the reverse direction of the forward delay array
261
from the detected position in the backward delay array
263
, so as to output a clock signal clksmd
253
. The clock signal clksmd
253
has a delay time of (Tclk−Tbuf2) from the input clock signal clkin
251
. The clock signal clksmd
253
from the synchronous mirror delay circuit is distributed to a predetermined circuit as a distribution clock signal clkout
254
at the clock buffer
265
. If the delay time of the clock buffer
265
is Tbufl, the delay time difference (Tdel1) between the input clock signal cikin
251
and the distribution clock signal clkout
254
becomes (Tclk−Tbuf2+Tbuf1). If the delay time difference Tbuf1 is the same between the replica of buffer
264
and the clock buffer
265
, the delay time difference between them becomes Tdel=Tclk. A signal synchronized with Mthe input clock signal can thus be supplied as a distribution clock signal. This distribution clock signal can be settled within several clock cycles after the operation is started.
In order to equalize both delay times (Tbuf2 of the replica of buffer
264
and Tbuf1 of the clock buffer
265
) as shown in
FIG. 44
, the replica of buffer
264
should be designed according to the clock buffer
265
. If the load of the clock buffer
265
is unknown or if the load of the clock buffer
265
is changed after the circuit is designed or if the load
266
is unknown or undefined, therefore, the replica of buffer
264
cannot compensate the delay time at this portion. In addition, no synchronous signal can be generated when the delay time of the clock buffer
265
is changed due to a change of the circuit characteristics caused by a manufacturing process and a temperature change during an operation.
The technique for considering changes of a load in the synchronous mirror delay circuit is described in “The Direct Detect Synchronous Mirror Delay (Direct SMD) for ASICs” IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE, pp511-514, 1998. In other words, the synchronous mirror delay circuit is not provided with any feed-back circuit, but provided two delay lines and one replica of delay circuit. The clock driver dummy circuit is omitted in the replica of delay circuit and a feed-back circuit is employed Ainstead of the dummy circuit. However, the document does not describe any concrete configuration of the synchronous mirror delay circuit. In addition, the synchronous mirror delay circuit can obtain output clock signals whose duty ratio is only 1/10 or so respectively. This is why the circuit cannot be employed for a system which uses both rising and falling of each clock signal.
SUMMARY OF THE INVENTION
Under such the circumstances, it is an object of the present invention to solve the problems of the conventional synchronous mirror delay circuit described above and provide a timing-control circuit device and a clock distribution system which can correspond to changes of an output load. More concretely, it is an object of the present invention to provide a timing-control circuit device and a clock distribution system which can supply a clock distribution signal kept synchronized in phase with an input clock signal even when the delay time of the clock signal is changed due to such a load as a clock buffer. The timing-control circuit device uses a synchronous mirror delay circuit.
Hereunder, some representative inventions disclosed in this specification will be described briefly.
The timing-control circuit (SMDF
14
) of the present invention receives such a first transfer signal (clkin
11
) as a reference clock signal, etc., thereby generating such a second transfer signal (clk
12
) as an internal clock, and further generating such a third transfer signal (clkout
13
) as an external clock, etc. through a buffer (BUF
15
). At this time, the timing-control circuit (SMDF
14
) receives a fed-back external clock signal, thereby generating an internal clock signal so as to establish the synchronization of phase between the external clock signal and the reference clock signal. Inside the timing-control circuit (SMDF
14
) are provided circuits (FDA
21
, MCC
22
, and REG
23
) for detecting a phase difference between internal clock and external clock, as well as a delay circuit (DCL
24
) for controlling the delay time. The delay circuit can change the delay time according to the detected phase difference. Consequen

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