Timing circuit with dual phase locked loops

Details Timing circuit with dual phase locked loops Timing circuit with dual phase locked loops

2006-02-28

2006-02-28

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S219000, C375S371000

Reexamination Certificate

active

07006590

ABSTRACT:
A timing circuit for generating clock signals, includes an acquisition digital phase locked loop with a wide capture range for closely following an input signal with its associated disturbances. An output digital phase locked loop having a slow response relative to the acquisition phase locked loop tracks an output of the acquisition phase locked loop to generate an output signal for the timing circuit.

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