Timing circuit and method for a compilable DRAM

Details Timing circuit and method for a compilable DRAM Timing circuit and method for a compilable DRAM

2001-06-13

2003-03-25

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100

Reexamination Certificate

active

06538932

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of dynamic random access memory (DRAM); more specifically, it relates to a compilable DRAM and a method for designing the compilable DRAM.
BACKGROUND OF THE INVENTION
A compilable DRAM is a DRAM generated by a DRAM compiler. A DRAM compiler is a computer program containing algorithms based on a methodology that can synthesize different memory configurations to satisfy a customer's needs for an embedded DRAM in their circuit design. Generally, these are custom designs for application specific integrated circuits (ASICs). The specific DRAM configuration is determined by the customers specification as to memory size, word width, number of words, and number of memory arrays. Compilable DRAMs are desirable because they are denser than SRAMs (static random access memory) and take up less space. In some cases, the technology (ground rules, materials, processes and performance specifications) of DRAMs may match the technology of other macros in the ASIC more closely than the technology of a SRAM.
FIG. 1
is a diagram of a portion of a DRAM device. In
FIG. 1
, DRAM device
100
is comprised of sets of memory units
105
, each memory unit containing multiple DRAM arrays
110
. DRAM arrays
110
are comprised of arrays of individual DRAM cells. The number of DRAM cells in each DRAM array
100
can range from just a few to many millions depending upon the specific application the DRAM device is designed for. DRAM devices
100
also include sets of wordline drivers
115
. Each wordline driver
115
drives wordline signals onto wordlines
120
. In general, each wordline
120
is comprised of a set of local wordlines connected to groups of DRAM cells within DRAM blocks
110
. Local wordlines are strapped together in series to form global wordlines that run the length of memory units
105
. There is one wordline driver for each DRAM unit
105
. All wordlines
120
in a given memory unit
105
, run through, and are coupled to memory cells in each DRAM array
110
of the memory unit. DRAM device
100
further includes sets of bitline drivers
125
. Each bitline driver drives data signals to bitline pairs
130
. Bitline pairs
130
run orthogonal to wordlines
120
. Bitline pairs
130
are coupled to memory cells in one DRAM array
110
of each memory unit
105
.
Because of the length of memory units
105
and the fact that wordlines
120
have a finite resistance, a signal impressed on any wordline of any wordline pair will arrive at the DRAM array
110
closest to wordline driver
115
before the signal arrives at the DRAM array farthest from the wordline driver. In advanced DRAM technology, the local wordline are usually formed polysilicon and the straps of metal. Since the metal straps have a sheet resistance of 0.12 ohms/sq. and polysilicon has a sheet resistance of about 300 to 400 ohms/sq. the wordline delay is mainly a function of the resistance/capacitance of the local wordlines for short memory units
105
. For longer memory units
105
, the delay becomes a complex function of metal and polysilicon delays.
FIG. 2
is a timing diagram for the DRAM device of FIG.
1
. In
FIG. 2
, a wordline signal
150
A is the signal reaching the closest DRAM array
110
and a wordline signal
150
B is the signal reaching the farthest DRAM array
110
. The difference in time between arrivals of the signal is wordline delay “D.” After a bitline charge delay “d
1
,” from wordline signal
150
A, during which a bitline
155
A signal and a bitline-not signal
165
A build charge, bitline/bitline-not amplifiers of the closest DRAM array
110
, turn on (set) to boost the signal voltage of the bitline and bitline-not signals. Similarly, after a bitline charge delay “d
2
,” from wordline signal
150
B, during which a bitline
155
B signal and a bitline-not signal
165
B build charge, bitline/bitline-not amplifiers of the farthest DRAM array
110
turn on (set) to boost the signal voltage of the bitline and bitline-not signals. Because of wordline delay “D,” the set times of the bitline/bitline amplifiers of the closest DRAM array
110
and the bitline/bitline-not amplifiers of the farthest DRAM array
110
must be delayed by the wordline delay “D.” In a fixed size DRAM this is not a significant problem as the length of wordlines pairs
120
are fixed and known so a delay device circuit can be designed to simulate the wordline delay “D” and then incorporated into the circuit design to delay turn on (set) of the bitline/bitline-not amplifiers of farthest DRAM array
110
, as well as all the intervening DRAM arrays, until the appropriate time. However, in a compilable DRAM, the length is not fixed or known ahead of time, so this approach is not very effective.
FIG. 3
is a schematic diagram of a method of setting timing in a static random access memory (SRAM) device. In
FIG. 3
, SRAM device
165
includes a closest SRAM array
170
A, a farthest SRAM array
170
B and a wordline driver
175
. Wordline driver
175
drives wordline signals onto a multiplicity of wordlines
180
running from closest SRAM array
170
A to farthest SRAM array
170
B. Wordlines
180
are coupled to memory cells in each SRAM array of SRAM device
165
. A multiplicity of closest bitlines
185
A run through closest SRAM array
170
A, orthogonal to wordlines
180
, and are coupled to cells in the closest SRAM array. A multiplicity of farthest bitlines
185
B run through closest SRAM array
170
B, orthogonal to wordlines
180
, and are coupled to cells in the farthest SRAM array. SRAM device
165
also includes a reference SRAM array
190
and a reference wordline driver
195
. Reference wordline driver
195
drives dummy wordline signals onto a reference wordline
200
. Reference wordline
200
has the same length and is otherwise a physical replica of wordlines
180
. The purpose of reference wordline
200
is to as act a resistive delay model of wordlines
180
. Coupled to reference wordline
200
, at the end opposite from reference wordline driver
195
, is sense device
205
. In this example, sense device
205
is a simple inverter. Sense device
205
is used to turn on (set) bitline amplifiers for farthest bitlines
185
B. If there are intervening SRAM arrays between closest SRAM array
170
A and farthest SRAM array
170
B, additional reference wordlines of appropriate length may be placed in reference SRAM array, with additional sense devices for setting bitlines in intervening SRAM arrays, attached thereto.
This approach does not work for an advanced technology compilable DRAM for two reasons. First, is the problem of the composition of wordlines. SRAM wordlines are comprised of master wordlines and local wordlines, each having drivers. In an SRAM, both master and local wordlines are metal and the delay is a straightforward low value metal RC delay (a metal wordline has a sheet resistance of about 0.12 ohms/sq.). As previously discussed, in a DRAM, the wordline is a metal/polysilicon combination with metal straps stitching together polysilicon local wordlines. Second, ground rules for wordlines in SRAM cells are generally larger than the ground rules for wordlines in a DRAM. This forces the use of dummy local wordlines to be placed outside the array of active memory cells for the photolithographic reasons described above. This problem is illustrated in FIG.
4
and described next.
FIG. 4
is an illustration of printed wordlines for an advanced DRAM device. Illustrated in
FIG. 4
, is an active local wordline set
210
is comprised of an outer active local wordline
215
and inner active local wordlines
220
. Also illustrated in
FIG. 4
, is a dummy local wordline set
225
. Dummy local wordline set
225
comprises an inner dummy local wordline
230
, a middle dummy local wordline
235
and an outer dummy local wordline
240
. Inner dummy local wordline
230
is most adjacent to outer active local wordline
215
. One purpose of dummy local wordline set is to mitigate proximity effects on wordlines in active local wordline set
210
. All of active local wordlines ar

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