Timing calibration pattern for SLDRAM

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique

Reexamination Certificate

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C713S401000

Reexamination Certificate

active

06889357

ABSTRACT:
Disclosed is an improved start-up/reset calibration apparatus and method for use in an SLDRAM memory device A 2Nbit calibration pattern which is based on a pseudo random sequence is used to calibrate the relative timing of data and a latching clock signal to ensure optimal operation of the memory device. In addition, during calibration of one data path, other nearby data paths may receive in phase, out of phase and/or both in phase and out of phase versions of the calibration pattern so that the data path under calibration is calibrated under conditions which more closely approximate random operating conditions.

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patent: 6636999 (2003-10-01), Yamada
Gillingham; “SLDRAM Architectural and Functional Overview”; SLDRAM Consortium, Aug. 29, 1997, pp. 1-14.

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