Timing calibration method and semiconductor device testing...

Details Timing calibration method and semiconductor device testing... Timing calibration method and semiconductor device testing...

2001-07-26

2003-04-29

Barlow, John (Department: 2863)

Data processing: measuring, calibrating, or testing

Calibration or correction system

Timing

C702S040000

Reexamination Certificate

active

06556934

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a timing calibration method of a semiconductor testing apparatus and also relates to a semiconductor device testing apparatus having the timing calibration function which can test a semiconductor device including memories, logic circuits and the like.
2. Description of the Related Art
FIG. 7
shows a briefly illustrated generally known semiconductor device testing apparatus. The semiconductor device testing apparatus comprises a computer system
10
operating as a controller of the semiconductor device testing apparatus, a pattern generator
11
, a pin data selector
12
, a waveform formatter group
13
, a timing calibrator group
14
, a driver group
15
, an output pin group
16
, a device power supply source
17
, a logical comparator
18
, a failure analysis memory
19
. A semiconductor device under test which is hereinafter referred to as DUT is turned into its operating state upon receipt of a power supply voltage from the device power supply source
17
, and test pattern signals (TPS) delivered to the output pin group
16
are supplied to input pins or input/output pins for both signal input and output use of DUT.
The pattern generator
11
outputs test pattern data (TPD) for a plurality of channels. These test pattern data are distributed to the respective input pins as respective pin data for DUT.
The waveform formatter group
13
includes waveform formatters (
13
-
1
,
13
-
2
,
13
-
3
, - - - ) the number of which is sufficient to cover the number of channels corresponding to the input pins of DUT. When a plurality of DUTs are simultaneously tested, waveform formatters, the number of which is equal to the number of devices multiplied by the number of channels, are to be provided. Each test pattern data distributed as each pin data is shaped to a test pattern signal (TPS) having a waveform that meets standard requirements (for example, amplitude value) of the semiconductor device to be tested DUT, and this test pattern signal is delivered via the timing calibrator group
14
(
14
-
1
,
14
-
2
,
14
-
3
, - - - ) and the driver group
15
(
15
-
1
,
15
-
2
,
15
-
3
, - - - ) to the output pin group
16
(P
1
, P
2
, P
3
, - - - ).
Now, hereinafter each signal transmission channel through which each test patter signal is delivered from the waveform formatter, via the timing calibrator and the driver to each output pin, is referred to as a test pattern signal transmission path of each channel of the semiconductor device testing apparatus.
In the case where DUT is a memory, the test pattern signal at the output pin is applied to input terminal of DUT and is written or stored in the memory of DUT. The test pattern signal thus written in DUT is then read out therefrom at its output terminal as output data (OPD) which is in turn compared with an expected value data (EPD) by the logical comparator
18
.
When a discordance is detected by the logical comparator
18
, an address of the memory at which the discordance is detected, the test pattern by which the discordance is caused, and the like are stored in the failure analysis memory
19
, and are utilized in a failure analysis, a failure relief processing, or the like.
Among test items of a semiconductor device to be tested DUT, there is a test for inspecting response characteristics of DUT, which includes, for example, an inspection of a marginal phase range in which DUT can maintain its operable condition by shifting the phase of the test pattern signal to be applied to an input terminal of DUT toward advancing direction or delaying direction from a reference phase position by varying timing of a timing signal generated by a timing generator (although not shown in the drawings), or another inspection of a marginal timing delay in an output timing of the read out data from a timing at which a read command signal is applied to DUT.
When the test of this type is performed, it is necessary that respective signal propagation time values for respective test pattern signal transmission paths each being constituted by a waveform formatter, a tuning calibrator, and a driver should be aligned to have a same constant value. A work for aligning the respective signal propagation time values of respective test pattern signal transmission paths to a constant value is referred to as a timing calibration. In order to perform this timing calibration mode, there is provided a specific arrangement including the timing calibrator group
14
, a pin selection device
21
, and a timing measurement device
22
.
FIG. 8
shows a previously developed testing apparatus within a facility of the Assignee of the present invention which shows a connection state of the testing apparatus in its timing calibration mode, wherein the pin selection device
21
is connected to a group
16
of output pins P
1
, P
2
, P
3
, - - - , and any one of the output pins in their output pin group
16
is selectively connected by the pin selection device
21
to the timing measurement device
22
.
As the timing measurement device
22
for use in the timing calibration mode, for example, an oscilloscope or any timing measurement means usually equipped in a semiconductor device testing apparatus of this type can be used.
In the timing calibration mode of the testing apparatus as shown in FIG.
8
, the pattern generator
11
generates a timing calibration pulse data, TPD which is designed to form a timing calibration pulse PT having a predetermined constant duration period at the respective waveform formatters.
The pin data selector
12
distributes the timing calibration pulse data TPD, from the pattern generator to the respective waveform formatters (
13
-
1
,
13
-
2
, - - - ), so that the timing calibration pulse (PT) is generated by each of the respective waveform formatters and is transmitted through respective test pattern signal transmission paths to the respective output pins (P
1
, P
2
, - - - ), respectively.
Now assuming one of the output pins, for example, P
1
in
FIG. 8
as a reference output pin.
The timing calibration pulse signals (PT) having the constant duration period as shown in
FIG. 9
is transmitted to the predetermined reference output pin, P
1
in
FIG. 8
via a reference test pattern signal transmission path which is composed of a series connection circuit of a waveform formatter
13
-
1
, a timing calibrator
14
-
1
, and a driver
15
-
1
, and is then selectively transmitted to the timing measurement device
22
by a pin selection device
21
.
FIG. 10
shows an example of internal circuit structure of the pin selection device
21
. In this example, there is shown a case of circuit structure in which the reference output pin P
1
of the output pin group
16
can be connected to the output terminal TOU by switching operations of relay switches RS
1
-
1
through RS
4
-
1
. In the example of
FIG. 10
, there is shown a state that the relay switches RS
1
-
1
, RS
2
-
1
, RS
3
-
1
and RS
4
-
1
are connected to a contact side (a), which is referred to as a pin selection path for the reference output pin P
1
in the pin selection device
21
.
In the case of using an oscilloscope as the timing measurement device
22
, a rising timing of the thus transmitted timing calibration pulse PT is measured using a scale on the lateral X axis that is a time axis on the display screen (OSD) of the oscilloscope, and that scale position is determined as a reference phase position (RPP). (See
FIG. 9
) The timing calibration pulses (PT) are transmitted to the respective remaining output pins P
2
, P
3
, - - - via the corresponding test pattern signal transmission paths and also selectively connected one after another to the oscilloscope. The corresponding delay time values of the timing calibrators
14
-
2
,
14
-
3
, - - - in the respective test pattern signal transmission paths for the remaining output pins P
2
, P
3
, - - - other than the reference output pin P
1
are adjusted to perform the timing calibration such that a rising timing of the outputted pulse sequence at each

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