Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-05-12
2008-11-11
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07451417
ABSTRACT:
A method of generating timing information for a circuit design can include determining static timing data for the circuit design and identifying a source of timing information for use in functional simulation of the circuit design. The method also can include updating the source of timing information to include at least a portion of the static timing data.
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Campbell Scott J.
Escobar Mario
Lujan Jaime D.
Manaker, Jr. Walter A.
Philofsky Brian D.
Bowers Brandon W
Chiang Jack
Cuenot Kevin
Hardaway Michael R.
Xilinx , Inc.
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