Timing analyzing method and apparatus for semiconductor...

Details Timing analyzing method and apparatus for semiconductor... Timing analyzing method and apparatus for semiconductor...

2006-10-02

2008-12-09

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07464355

ABSTRACT:
A method for analyzing timing in a semiconductor integrated circuit device with multi-corner conditions including a best-case corner condition and a worst-case corner condition. The best-case corner condition and the worst-case corner condition each include a temperature condition, with each temperature condition being a high temperature condition or a low temperature condition. The method includes storing in a temperature characteristic coefficient table a temperature characteristic coefficient for each of temperature-reversed corner conditions that are generated by selectively reversing the temperature conditions of the best-case corner condition and the worst-case corner condition, and performing timing analysis under said temperature-reversed corner conditions based on a gate delay and net delay calculated under the best-case corner condition and the worst-case corner condition and the temperature characteristic coefficient.

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