Timing analysis of a mapped logic design using physical delays

Details Timing analysis of a mapped logic design using physical delays Timing analysis of a mapped logic design using physical delays

2011-02-08

2011-02-08

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S113000

Reexamination Certificate

active

07886256

ABSTRACT:
Approaches for determining a static timing analysis of a logic design are disclosed. Physical delay arcs of a plurality of physical elements of an integrated circuit specify respective propagation delays from inputs of the physical elements to outputs of the physical elements. Logic components of the logic design are mapped to selected ones of the physical components of the physical elements. For each of the logic components, the logic delay arcs are determined from the physical delay arcs. Each logic delay arc for each logic component specifies a propagation delay from an input of the logic component to an output of the logic component. A static timing analysis of the logic components is performed using the logic delay arc, and data from the timing analysis is output.

REFERENCES:
patent: 7092865 (2006-08-01), Burnley et al.
patent: 7246340 (2007-07-01), Van Antwerpen et al.
patent: 7594211 (2009-09-01), Tian et al.

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