Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-07-26
2002-03-05
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06353916
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a timing analysis method in logic LSI design and more specifically to a timing analysis method used to verify the operating speed of semiconductor integrated circuits.
In recent deep sub-micron generations of LSI semiconductor integrated circuits, the interconnection capacitance has been forming an increasingly important factor in determining the circuit operating speed. Interconnection capacitances are roughly classified into two groups: capacitances between signal nodes through which a signal current flows and power supply or ground and coupling capacitances between signal nodes. In recent years, the fine pattern process has increased the percentage of the node-to-node coupling capacitance relative to the node-to-power supply (ground) capacitance. These capacitances will be described below.
FIG. 1
is a circuit diagram illustrating device-to-device interconnection capacitances. A node N
100
that interconnects inverters IV
100
and IV
102
and a node N
102
that interconnects inverters IV
104
and IV
106
are formed in close proximity to each other. In this case, coupling capacitance Cc is present between the nodes N
100
and N
102
. In addition, ground capacitance Cg exists between the node N
100
and ground.
As the demand has increased for incorporating a system in its entirety into a single chip, the circuit scale of semiconductor integrated circuits has increased. For this reason, the technique of verifying the performance of chips that are increasing in circuit scale, especially their operating speed, has shifted from dynamic simulation requiring an enormous amount of verification time to static simulation allowing faster processing.
With conventional static timing analysis for semiconductor integrated circuits, it is impossible to compute the delay time associated with a certain node with coupling capacitance present between that node and another node in mind. This is due to the property of the static timing analysis that, at the time of analysis of a certain node, the potential at another node is unknown.
Thus, the static timing analysis is made heretofore in accordance with the following approaches.
A first approach is to neglect coupling capacitance.
FIG. 2
is an equivalent circuit illustrating inter-device interconnection capacitance when the coupling capacitance is neglected. As shown in
FIG. 2
, a node N
100
that interconnects inverters IV
100
and IV
102
and a node
102
that interconnects inverters IV
104
and IV
106
are formed in close proximity to each other. In this case as well, ground capacitance Cg is associated with the node N
100
to be analyzed.
A second approach is to double the value of coupling capacitance Cc and add it to the ground capacitance.
FIG. 3
shows an equivalent circuit in such a case. As shown in
FIG. 3
, a node N
100
that interconnects inverters IV
100
and IV
102
together and a node
102
that connects inverters IV
104
and IV
106
together are formed in close proximity to each other. In this case, ground capacitance Cg and capacitance
2
Cc twice the coupling capacitance Cc are associated with the node N
100
to be analyzed.
A third approach is to convert the coupling capacitance Cc to ground capacitance with its value maintained.
FIG. 4
shows an equivalent circuit in such a case. As shown in
FIG. 4
, a node N
100
that interconnects inverters IV
100
and IV
102
and a node
102
that interconnects inverters IV
104
and IV
106
are formed in close proximity to each other. In this case, ground capacitance Cg and coupling capacitance Cc are associated with the node N
100
to be analyzed.
However, the conventional approaches have the following problems.
In the first approach, the coupling capacitance is neglected. This supposes that, as shown in
FIG. 5
, the potential at node N
102
varies (falls or rises) in the same direction as and simultaneously with the potential at the node N
100
to be analyzed. Thus, the calculated delay time becomes less than the actual delay time except when the potentials at the two nodes vary simultaneously in the same direction.
In the second approach, the coupling capacitance Cc is doubled and then added to the ground capacitance Cg. This supposes that, as shown in
FIG. 6
, the potential at node N
102
varies (falls or rises) in the opposite direction to and exactly simultaneously with the potential at the node N
100
to be analyzed. Thus, except when the potentials at the two nodes vary simultaneously in opposite directions, the calculated delay time becomes more than the actual delay time.
In the third approach, the coupling capacitance Cc is added as it is to the ground capacitance Cg. This supposes that, as shown in
FIG. 7
, the potential at the node N
102
is fixed. Thus, except when the potential at the node N
102
is fixed, the calculated delay time becomes less than or more than the actual delay time.
That is, the conventional static timing analysis requires additional margin because the effect of the coupling capacitance cannot be reflected precisely. On the other hand, although conditions have been satisfied on static timing analysis, they may sometimes not be satisfied on actual chips.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a fast and precise timing analysis method for semiconductor integrated circuits which permits the effect of coupling capacitance between interconnections to be reflected accurately.
According to a first aspect of the present invention, there is provided a timing analysis method for semiconductor integrated circuits comprising the steps of: determining maximum capacitance and minimum capacitance for each of nodes on a circuit; making static timing analysis, using the maximum capacitance and minimum capacitance, of paths comprising one or more of the nodes on the circuit to classify the paths into conformable paths that satisfy a predetermined constraint, nonconformable paths that do not satisfy the constraint, and undecided paths that belong to neither the conformable paths nor the nonconformable paths; and making dynamic timing analysis of the undecided paths.
With this timing analysis method, the maximum capacitance and minimum capacitance are determined for each node on a circuit. Static timing analysis is first made using the maximum capacitance and minimum capacitance to classify paths into conformable paths that satisfy a predetermined constraint, nonconformable paths that do not satisfy the constraint, and undecided paths that belong to neither the conformable paths nor the nonconformable paths. Dynamic timing analysis is then made of the undecided paths to allow them to fall into either conformable paths or nonconformable paths. The use of the dynamic timing analysis only for the paths that cannot be distinguished by the static timing analysis allows the time required for timing analysis to be reduced and precision analysis to be made.
According to a second aspect of the present invention, there is provided a timing analysis method for semiconductor integrated circuits comprising the steps of: determining maximum capacitance and minimum capacitance for each of nodes on a circuit; making static timing analysis of data nodes that carry data signals and clock nodes that carry clock signals with the maximum capacitance selected for the data nodes and the minimum capacitance selected for the clock nodes; classifying, on the basis of the result of the static timing analysis, paths comprising one or more of the nodes on the circuit into conformable paths that satisfy a setup constraint and undecided paths that do not belong to the conformable paths; and making dynamic timing analysis of the undecided paths.
With this timing analysis method, the maximum capacitance and minimum capacitance are determined for each node on a circuit. Static timing analysis is first made using the maximum capacitance and minimum capacitance to classify paths into conformable paths that satisfy a setup constraint and other paths that cannot be decided by the static tim
Kabushiki Kaisha Toshiba
Whitmore Stacy
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