Timing adjusting circuit and semiconductor memory device

Details Timing adjusting circuit and semiconductor memory device Timing adjusting circuit and semiconductor memory device

2005-04-05

2005-04-05

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S191000

Reexamination Certificate

active

06876568

ABSTRACT:
In a memory cell array, a plurality of memory cells having ferroelectric capacitors are arranged. A plurality of sense amplifier circuits amplifies the potential of the bit line of each memory cell. A column decoder outputs activation signals to activate the sense amplifier circuits. Timing adjusting circuits have a ferroelectric capacitor for timing adjustment in transmitting the activation signals output from the column decoder to the sense amplifier circuits.

REFERENCES:
patent: 6707702 (2004-03-01), Komatsuzaki
patent: 9-259590 (1997-10-01), None

Affiliated with

Also associated with

Rating

Timing adjusting circuit and semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Timing adjusting circuit and semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing adjusting circuit and semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3438533