Timing abstraction and partitioning strategy

Details Timing abstraction and partitioning strategy Timing abstraction and partitioning strategy

2006-10-24

2006-10-24

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07127692

ABSTRACT:
The present invention is directed to a timing abstraction and partitioning strategy for integrated circuit design. A method for designing an integrated circuit may include monitoring user interaction with logical blocks during a function design process of an integrated circuit. Indications of timing properties are derived during the functional design process.

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Hodges et al., Computer integrated manufactirung (semiconductor processing), Sep. 1989, Electronic manufactirung technology symposium, Proceedings, Seventh IEEE/CHMT International, pp. 1-3.

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