Timestamp-based all digital phase locked loop for clock...

Details Timestamp-based all digital phase locked loop for clock... Timestamp-based all digital phase locked loop for clock...

2006-04-12

2010-02-02

Pathak, Sudhanshu C (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S376000, C375S371000, C375S355000, C375S326000, C370S497000, C331S179000, C331S016000, C713S400000

Reexamination Certificate

active

07656985

ABSTRACT:
A timestamp-based all digital phase locked loop is utilized for clock synchronization for Circuit Emulation Service (“CES”) over packet networks. The all digital phase locked loop at a CES receiver includes a phase detector, a loop filter, a digital oscillator and a timestamp counter. The all digital phase locked loop enables the CES receiver to synchronize a local clock at the receiver with a clock at a CES transmitter, where indications of transmitter clock signals are communicated to the receiver as timestamps. The phase detector is operable to compute an error signal indicative of differences between the timestamps and a local clock signal. The loop filter is operable to reduce jitter and noise in the error signal, and thereby produce a control signal. The digital oscillator is operable to oscillate at a frequency based at least in-part on the control signal, and thereby produce a digital oscillator output signal. The timestamp counter operable to count pulses in the digital oscillator output signal, and output the local clock signal.

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U.S. Appl. No. 11/279,410; Claims; pp. 25-28; filed Apr. 2006.

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