Timer with fixed and programmable interrupt periods

Details Timer with fixed and programmable interrupt periods Timer with fixed and programmable interrupt periods

1999-01-29

2001-04-03

Ray, Gopal C. (Department: 2181)

Electrical computers and digital data processing systems: input/

Interrupt processing

Programmable interrupt processing

C710S260000

Reexamination Certificate

active

06212594

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic systems utilizing interrupts. More particularly, the present invention relates to a method and apparatus for generating two programmable interrupts, with one of these interrupts being triggered within the other. Both interrupts are triggered within the maximum time interval of a timer.
2. The Background Art
Modern integrated circuits utilize clock signals, interrupts, and signals having high states and low states in order to operate properly.
Interrupts are signals which are typically related to microprocessors, and usually indicate that a particular action needs to occur. For instance, an interrupt may be asserted when a device attached to the system containing the microprocessor needs to be serviced. In another instance, an interrupt may be asserted when an interval of time has passed.
Occasionally, when transmitting information from one circuit to another, it is necessary to encode that information in some way. However, the conventional methods are sometimes inadequate for the job. The present invention provides a method and apparatus for providing two programmable interrupts which may be used in many ways; to transmit numerical values from one circuit to another, to digitally transmit voltage or current data, etc.
SUMMARY OF THE INVENTION
A method for causing two programmable interrupts to take place is described herein, using a counter having an output having an adjustable period, a first register which controls the length of the total period of the counter, a second register which controls the length of the second portion of the period of the counter cycle, the steps in the method comprising loading the first register with a first value, loading the second register with a second value, simultaneously causing the counter to count down from said first value to zero, and causing an output of the timer to be a binary “0” during a first portion of the counter period, comparing the value of the first register to the value of the second register, causing, when the value of the first register and the second register are equal, said output of the counter to be a binary “1” until the value of the first register becomes zero.


REFERENCES:
patent: 5307459 (1994-04-01), Petersen et al.
patent: 6064646 (2000-05-01), Shal et al.

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