Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
2001-06-12
2004-11-30
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
C358S001150, C714S044000
Reexamination Certificate
active
06826706
ABSTRACT:
FIELD OF THE INVENTION
This invention pertains to a system for evaluating operational parameters, and in particular for evaluating various timers and timeout conditions.
BACKGROUND OF THE INVENTION
Evaluating timers and timeout conditions in circuitry usually requires setting up timing circuitry specifically designed to evaluate the timer or the timeout condition. This may include providing a signal to increment a timer and circuitry to provide notice in the event that an error condition has occurred, for example, the timer overflows indicating that a time period has been exceeded or has not been achieved. The timing circuitry may also include a reset signal that resets the timer in the event that the proper conditions have been met.
It would be advantageous to have pre-designed circuitry for this type of evaluation that simply requires setting a few individual parameters, or that even includes a standard set of parameters used for evaluation. Such a system would enable the evaluation of various timeout conditions by allowing the assessment of various timers upon the occurrence of a time out. It would also be advantageous if this could be accomplished without having to set up individual circuits and fixed values for every timer or timeout condition to be evaluated or assessed. It would also be advantageous if the circuitry were capable of evaluating multiple timers or timeout conditions and recording the timed values in the event of a timeout, so that a snapshot of a failing condition may be observed after the failure.
OBJECTS AND ADVANTAGES OF THE INVENTION
It is a first object and advantage of this invention to provide an improved system for evaluating timeout conditions that may occur in a system.
It is a further object and advantage of this invention to provide an improved system for evaluating a timeout condition by further evaluating at least one timer in the event of such a timeout condition by providing circuitry with specific timing functions and predetermined timing conditions which may be adjusted according to the timers and timeout conditions being evaluated.
It is a further object and advantage of this invention to provide circuitry which allows for setting initial or special conditions that must be met before an evaluation or evaluations may begin, or to define evaluation periods.
It is a further object and advantage of this invention to provide circuitry which allows for setting conditions upon which an evaluation or evaluations will terminate, and the values of timers associated with certain timers and timeout conditions are recorded.
It is a further object and advantage of this invention to provide circuitry which allows for varying a common timer clock to match evaluation requirements.
SUMMARY OF THE INVENTION
The foregoing and other problems are overcome and the objects of the invention are realized by methods and apparatus in accordance with embodiments of this invention.
An apparatus for evaluating at least one timer in the event of a timeout condition in a system is disclosed that includes circuitry that generates an indication that certain system conditions have occurred, clock circuitry, enabled by the indication, that generates a timeout counter enable signal, and a number of timer units, coupled to the clock circuitry, where each of the timer units is incremented by an incrementing signal and reset by a monitored signal that represents conditions in the system. The invention includes comparison circuitry coupled to the timeout units, such that when at least one of the timer units reaches a predetermined count, the count, or the maximum count reached to this point, of each of the timer units is stored.
REFERENCES:
patent: 5471564 (1995-11-01), Dennis et al.
patent: 5537541 (1996-07-01), Wibecan
patent: 5577213 (1996-11-01), Avery et al.
patent: 5740497 (1998-04-01), Yamada et al.
patent: 5745663 (1998-04-01), Takagi
patent: 5870533 (1999-02-01), Takagi
patent: 5935262 (1999-08-01), Barrett et al.
“Realtime Throughput Measurement,” IBM Technical Disclosure Bulletin, Mar. 1984, pp. 5688-5689.
International Buniess Machines Corporation
Lee Thomas
Ohlandt Greeley Ruggiero & Perle LLP
Reid Scott W.
Wang Albert
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