Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
1999-05-07
2002-02-19
Heckler, Thomas M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
Reexamination Certificate
active
06349388
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to timers for processor-oriented systems, and more particularly to a timer processing engine for supporting multiple virtual minimum time timers.
2. Description of the Related Art
As embedded applications become more complex, micrcontrollers have experienced a superintegration of memory and peripheral blocks, rendering chip resources even more valuable. The embedded applications industry has responded to superintegration with an effort to provide just enough silicon to microcontrollers to achieve the contemplated functionality. Implementation strategies for minimizing total silicon real estate while maintaining acceptable levels of performance are thus needed.
In large or protocol intensive applications for processor-oriented systems, numerous timers are used to provide reset functionality, interrupt generation functionality, event triggering functionality, and other timing functions. During the execution of these applications, an operating system frequently checks the states for numerous timers. This polling of numerous timers has significantly contributed to software or processor overhead in processor-oriented systems.
Many timers for processor-oriented systems are minimum time timers. A minimum time timer is a way of indicating whether a particular time period has passed, as opposed to a timer for measuring the duration between events or the duration of events. In processor-oriented systems, a hardware platform has supported a limited number of minimum time timers, typically two to five minimum time timers.
A basic minimum time timer has included a counter, a set of registers, a comparator, and other circuitry. A conventional approach to providing an additional minimum time timer within a processor-oriented system has been to supply another counter, set of registers, comparator, and other circuitry. Adding minimum time timers to processor-oriented systems has thus involved hardware duplication. In an effort to minimize hardware overhead allocated for timing functions, processor-oriented systems have been limited to a relatively small number of minimum time timers.
SUMMARY OF THE INVENTION
Briefly, the present invention provides a timer processing engine for supporting multiple virtual minimum time timers. The plurality of virtual minimum time timers of the timer processing engine includes a timer data structure suitable to store the timer states of a plurality of virtual minimum time timers. Each timer state may include a last time value indicating the last time a timer was processed, an elapsed time value indicating the length of time a timer has been running, a terminal time value indicating a time at which a timer is to expire, and a set of attributes for indicating how a timer is to be processed. The timer states could be arranged in a variety of ways such as, for example, a linked list from a timer state with the shortest terminal time value to a timer state with the longest terminal time value. A timer state machine of the timer processing engine processes the timer states.
The plurality of virtual minimum time timers further includes a free running counter for providing a current time of the timer processing engine and a comparator for maintaining the timer states. An interrupt generator of the timer processing engine may selectively provide interrupt signals in response to the timer states.
In a disclosed embodiment, a timer state may be processed by the timer state machine in the following manner. When a virtual minimum timer begins running, the running attribute for the timer is set to a first predetermined state. When the timer state machine detects that a running attribute for a virtual minimum time timer is set to the first predetermined state, then an elapsed timer value for the virtual minimum time timer is incremented by the difference between the current time derived from the free running counter and a last time value for the virtual minimum time timer. If the timer state machine detects that the elapsed time value for the virtual minimum time timer is greater than or equal to the terminal time value for the virtual minimum time timer, then the running attribute for the virtual minimum time timer is set to a second predetermined state. If the timer state machine detects that a restart attribute for the virtual minimum time timer is set to a third predetermined state, then the elapsed time value for the virtual minimum time timer is set to a predetermined initial value, the last time value for the virtual minimum time timer is set to the current time, and the running attribute for the virtual minimum time timer is reset to the first predetermined state.
In accordance with the present invention, the timer processing engine provides a scalable approach to supporting an arbitrarily large number of timers and reduces the typical processor overhead and hardware overhead involved in managing timers.
REFERENCES:
patent: 4160154 (1979-07-01), Jennings
patent: 4367051 (1983-01-01), Inoue
patent: 5023771 (1991-06-01), Kishi
patent: 5297275 (1994-03-01), Thayer
patent: 5659720 (1997-08-01), Fiacco et al.
patent: 5975739 (1999-11-01), Katayama et al.
Advanced Micro Devices , Inc.
Akin Gump Strauss Hauer & Feld & LLP
Heckler Thomas M.
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