Timer lockout circuit for synchronous applications

Details Timer lockout circuit for synchronous applications Timer lockout circuit for synchronous applications

2007-05-22

2007-05-22

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S194000, C327S261000, C327S276000

Reexamination Certificate

active

11363678

ABSTRACT:
A SDRAM. The SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and means for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.

REFERENCES:
patent: 5841707 (1998-11-01), Cline et al.
patent: 6353573 (2002-03-01), Koshikawa
patent: 6415402 (2002-07-01), Bishop et al.
patent: 6434082 (2002-08-01), Hovis et al.
patent: 6507526 (2003-01-01), Ohtake
patent: 6538933 (2003-03-01), Akioka et al.
patent: 2003/0185075 (2003-10-01), Park et al.
patent: 2005/0149779 (2005-07-01), Bleakley

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