Time synchronizing method for switching system

Details Time synchronizing method for switching system Time synchronizing method for switching system

1999-06-30

2002-10-29

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C710S058000, C709S241000, C713S400000, C368S010000

Reexamination Certificate

active

06473866

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a switching system, and more particularly to a time management method for a switching system.
2. Description of the Conventional Art
Generally, time of a switching system must be synchronized with International Standard Time. However, since the switching system has no synchronizing apparatus, an indirect way is applied. For example, a referential time (TDC: year, month, day, time, minute and second) of the switching system is set in accordance with a hardware HW time supplied from a time generating apparatus, a software SW time which is maintained by a real time clock (RTC) of each processor and a user time supplied by an operator.
FIG. 1
illustrates a time management apparatus for the conventional switching system.
As shown therein, the time management apparatus for the conventional switching system includes an OMP (operating and maintenance processor)
100
, an OMDC (operating and maintenance device controller)
200
, an HW time device
300
, and an MP (maintenance processor)
400
.
Particularly, the OMP
100
which operates and maintains the switching system determines a system time and periodically checks the time concordance using an SCM (system clock management), a system time management master. Also, the OMP
100
distributes the system time which has been determined in the system time determining process and periodical time concordance checking process to the MP
400
.
The OMDC
200
controlling and checking an HW time is connected with the OMP
100
through an IPC (inter processor communication)
10
and connected with the HW time device
300
through a DA (data access)-bus, accesses the HW time device
300
in accordance with an HW time request of the OMP
100
, and reports the accessed HW time to the OMP
100
.
The MP
400
consisting of an SNP (switching network processor)
40
and a plurality of SSPs (switching subsystem processors)
40
-
1
~
40
-n is connected with the OMP
100
through IPC links
11
~
17
. The description of the connection and operation of the IPC links will be omitted since it is irrelevant to the time management operation. The SSPs
40
-
1
~
40
-n carry out user/trunk matching and time switching operations and the SNP
40
performs space switching of outputs of the SSPs
40
-
1
~
40
-n and supplies the resultant outputs to a plurality of highways. Here, the number of SSPs
40
-
1
~
40
-n connected with the SNP
40
can be up to 32 at its maximum in consideration of the highways. In addition, the SNP
40
and the SSPs
40
-
1
~
40
-n are respectively provided with the SCM block of itself and set its own SW time in accordance with system time which is distributed by the OMP
100
.
With reference to
FIG. 1
, the operation of the time management apparatus for the conventional switching system will now be described.
In the initial start (or restart) of the system, the SCM block of the OMP
100
requests the OMDC
200
through the IPC line
10
to send the HW time, and the OMDC
200
access the HW time device
300
through the DA-bus and reports the HW time to the OMP
100
. When receiving the HW time from the OMDC
200
, the SCM block of the OMP
100
sets the HW time as an initial system time and then distributes the initial system time to the MP
400
through the IPCs
11
~
17
. However, if not receiving the HW time from the OMDC
200
due to defect of the HW time device
300
, the SCM block of the OMP
100
sets a predetermined time which is set by a user as the initial system time and distributes the initial system time to the MP
400
. Accordingly, the SCM blocks of the SNP
40
and the SSPs
40
-
1
~
40
-n of the MP
400
respectively set the time (SW time) of its own in accordance with the initial system time which is distributed from the OMP
100
. When the initial system time is set, the SCM block of the OMP
100
periodically resets the system time with reference to the HW time, the OMP time and the MP time in order, and distributes the reset system time to the MP
400
, so that the times of the switching system concur.
Now, the time management method of the conventional switching system will be described with reference to FIG.
2
.
Setting of Initial System Time
FIG. 2
is a flowchart illustrating setting of an initial system time in the system initial start (or restart). The system time management master is the SCM block of the OMP
100
. The SCM block request the HW time to the OMDC
200
when starting the system, the OMP
100
or the SCM block thereof, and registers a time-out signal of 5 seconds with an OS (operation system) (S
1
, S
2
). When receiving the HW time from the OMDC
200
before the time-out signal is inputted, the SCM block determines whether the received HW time has a normal time value (S
3
, S
4
) by checking time data (year, month, day, time, minute, second) of the HW time. For example, the normality of the HW time is determined by checking whether the time data is under 24 and minute and second data are respectively under 60. When the HW time has the normal time value, the SCM block sets the received HW time as the initial system time (the initial system time=the HW time).
Meanwhile, when if the HW time is not outputted from the OMDC
200
until the time-out signal is supplied from the OS (S
6
) or the HW time has an abnormal time value in the step S
4
, the SCM block outputs an alarm message and then sets the time set by the user as the initial system time (the initial system time=the user time) (S
7
). Once the initial system time is set, the SCM block distributes the initial system time to the MP
400
(S
8
), and the SNP
40
and SSPs
40
-
1
~
40
-n of the MP
400
respectively set the time of itself (SW time) as the initial system time and process all the functions, for example, metering, related with the time on the basis of the SW time. Further, the SCM block registers a cycle signal Cycle_sig of a 1 minute cycle with the OS to periodically check the time concordance (S
9
).
Periodical Time Concordance Checking
FIGS. 3A through 3D
are flowcharts illustrating checking of the time concordance with reference to the HW time, the OMP time and the MP time.
As shown therein, when the initial system time is set, the SCM block of the OMP
100
operates (is interrupted) in a 1 minute cycle in accordance with the cycle signal Cycle_sig and thus resets the system time referring to the HW time, the SW time of the OMP
100
or the SW time of the MP
400
. That is, the SCM block compares in order the HW time with the OMP time, the HW time with the MP time, the OMP time with the MP time and the MP times with each other, thereby determining the system time, because the reliability of the time is in order of the HW time, the OMP time and the MP time. Further, when the above processes are all failed, the OMP time is set as the system time. When the system time is reset, the SCM block distributes the reset system time to the MP
400
, and thus periodically checks the time concordance by making the times of the dispersed processors concur with each other, that is, the SNP
40
and the SSPs
40
-
1
~
40
-n of the MP
400
.
More specifically,
FIG. 3A
is a flowchart illustrating the operation of comparing the HW time with the OMP time and thus determining the system time. As shown therein, The SCM block of the OMP
100
which operates in the 1 minute cycle in accordance with the cycle signal Cycle_sig requests the HW time to the OMDC
200
and registers the time-out signal with the OS (S
10
, S
11
). When receiving the HW time from the OMDC
200
, the SCM block stores the received HW time and checks whether the HW time has the normal time value (S
13
). When the HW time is normal, the SCM block computes the time difference between the time (the OMP time) maintained by the RTC of itself and the HW time (S
13
, S
14
) and determines whether the computed time difference is a predetermined value (3 seconds) and below (S
15
). If the time difference is the 3 seconds and below, the SCM block resets the corresponding HW time as the s

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