Time switching circuit of synchronous super high speed...

Details Time switching circuit of synchronous super high speed... Time switching circuit of synchronous super high speed...

1998-09-15

2002-04-23

Olms, Douglas (Department: 2661)

Multiplex communications

Channel assignment techniques

Combining or distributing information via time channels...

C370S412000, C370S465000, C370S505000, C370S509000

Reexamination Certificate

active

06377586

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a switching circuit, and more particularly, relates to a memory saving type time switching circuit of a synchronous super high speed transmission apparatus for reducing required memory by switching data considering data properties which is received by the synchronous super high speed transmission apparatus.
2. Description of the Related Art
Recently, research for information communication networks started. One field of this research is a B-ISDN (Integrated Services Digital Network).
The B-ISDN (Integrated Services Digital Network) includes an User Network Interface (hereinafter referred to as a UNI) and a Network Node Interface (hereinafter referred to as NNI) for broadband service.
The communication hierarchy used for these two interfaces was unified to a SDH(Synchronous Digital Hierarchy) from American and European types around 1990. In the SDH, subscribers' data is multiplexed and transmitted through a communication line of an STM-1(Synchronous Transport Module, hereinafter it will be referred to as a STM) to an STM-4, and switched according to the SDH. Generally, signals of the STM-1 are multiplexed by 8 bits (1 byte) in turn, and such a multiplexing method is called byte interleaving.
FIG. 1
illustrates a whole aspect of a synchronous multiplexing structure related to the hierarchy signals in the SDH and the numerals in parentheses in
FIG. 1
illustrate the number of signals required to related multiplexing. The synchronous multiplexing process is illustrated in a dotted-box represented with SM (Synchronous Multiplexing) and an asynchronous multiplexing process is illustrated in a left-sided dotted-box represented with AM (Asynchronous Multiplexing).
The first step of the synchronous multiplexing process is that each hierarchy signal is mapped in a predetermined container(C). At this time, a bit-unit positive, zero and negative justifications, or positive justification are used for synchronizing. When a section overhead is added to a container, it becomes a VC (Virtual Container) and when a pointer (PTR) is added to a VC, it becomes a TU (Tributary Unit). But, in the case of a VC-3 and a VC-4, they are directly mapped to the STM-1 omitting other VC, the TU becomes an AU(Administrative Unit). At this time, numeral m (=1, 2, 3, 4) attached to each signal unit represents that the bit ratio of each signal unit corresponds to a DS-m grade. If m=1, it subdivides into 11 and 12, respectively, and represents a bit ratio corresponding to North American type DS-1 and European type DS-1E. But, the bit ratio becomes n times of 152.52 Mbps in the STM-n.
In the TU-1(TU-11 or TU-12), it grouped each four and multiplexed to the VC-3 and the VC-4 as a TUG(Tributary Unit Group) type. The TU-2 and the TU-3 are regarded the same as the TUG-2 and the TUG-3 as the same rank, respectively. The VC-3 can be multiplexed to the VC-4 via TU-3 or directly multiplexed to the AU via AU-3. An AUG (Administrative Unit Group) is regarded as AU-4 as the same rank and it becomes the STM-n signal when a SOH (Section Overhead) is attached after multiplexing n units of the AUGs.
An example of synchronous multiplexing is shown in FIG.
2
.
FIG. 2
illustrates a multiplexing process for paths of DS-1/C-11/VC-11/TU-11/TUG-2/TUG-3/VC-4/AU-4/AUG/STM-n that is illustrated using the thick line in FIG.
1
. In
FIG. 2
, the DS-1 signal is first mapped to the C-11, the VC-11 is obtained by attaching a VC-11 POH to the C-11 and the TUG-2 is obtained by attaching a TU-11 PRT to the VC-11 and multiplexing them by four.
In the TUG-2 signal of
FIG. 2
, TU-11 PRT of each TU-11 is grouped with each TU-11 PRT. The TUG-3 is obtained by multiplexing seven units of the TUG-2s and attaching an FOH (Fixed Overhead) in front of seven units of the TUG-2. The VC-4 is obtained by multiplexing three units of the TUG-3 and attaching the FOH and the VC-4 POH (Section Overhead) in front of the three units of the TUG-3. Therefore, the VC-4 signal is the same as multiplexing 21 units of the TUG-2 and attaching the VC-4 POH and the FOH.
In multiplexing results, 84 units of the TU-11s are individually accessible on the VC-4. In the VC-4, the FOH is simply used for adapting the VC-4 size as an overhead. The AU-4 is obtained by attaching the AU-4 PRT in front of the VC-4 and it is the same as the AUG signal. The STM-n is obtained by multiplexing n units of the AUGs and attaching a section overhead on the AUG.
The contents of above-mentioned SDH hierarchy are easily understood by those who are skilled in the “Synchronous Digital Hierarchy Bit Rates CCITT Recommendation G.707” of 1992.
A Network Node Apparatus such as a Synchronous Multiplexer (SM), an ADD/Drop Multiplexer (ADM), a Digital Cross-Connect System (DCS), an Interworking Unit (IWU) and an Interface Unit (IFU) is used in a synchronous transmission network. The ADM and the DCS can give flexibility to network operation by branching and coupling synchronous transmission signals.
The late-mentioned preferred embodiments of the present invention will describe data switching of a light transmission apparatus working as an ADM.
Meanwhile, data multiplexing of the synchronous digital transmission network will be described hereinafter. Voice data of the synchronous digital transmission network generally transmits 8000 units of eight bit(1 byte) information. So, its transmission speed is 64 kbps. One line is an 8-bit unit and, especially, the time required for transmitting one byte in the voice data is called the time slot. In a digital network, a plurality of lines are sequentially multiplexed per eight bit.
FIG. 3
illustrates multiplexing four lines and transmitting data and one byte is transmitted by every four periods. Like this, the frame period(To) is a period for multiplexing lines and returning to an initial state.
Because multiplexed signals wait for their order per line, data switching is executed by changing their order using a predetermined method. For example, like
FIG. 3
, data switching is executed by storing received digital signals in a memory, sequentially reading the digital signals to an outputting port to be transported and outputting them.
Referring to
FIG. 4
, the PM5371 TUDX system of the PMC-Sierra Company, generally used system for a digital switching system, includes a byte stream input portion
41
that receives byte stream that is to be switched. A switching portion
42
that temporarily stories received input stream for switching. A sequence control portion
44
that reads stored data of the switching portion
42
according to a predetermined sequence. An output formatter
45
that realigns read data of the sequence control portion
44
for outputting to an output terminal (not shown here). At this time, the switching portion
42
needs memories
43
of square-law number of the byte stream input port.
Referring to
FIG. 4
, operation of digital switching type will be described hereinafter. A byte (eight-bits) received data that is to be switched is consequently received and temporarily stored to memories
43
in the switching portion
42
. The sequence control portion
44
inputs control signals about data for switching received data to the switching portion
42
and the output formatter
45
, reads received data from the byte stream input portion
41
in the memories
43
of the switching portion
42
and outputs to the output terminal (not shown here).
The basic algorithm applied to data switching with reference to
FIG. 4
includes the received data such as A, B, C, D . . . that are to be switched and temporarily stored in the switching portion
42
. Reading address values for data that are to be switched are received by the switching portion
42
. The temporarily stored data that is to be switched is read according to the reading address values and output to the output terminal. In other words, if the received data sequence is A, B, C and D, data is respectively switched and output D, C, B and A. The data switching method using such an algorithm is c

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