Time switch with the control memory

Details Time switch with the control memory Time switch with the control memory

1998-05-21

2001-07-31

Ton, Dang (Department: 2732)

Multiplex communications

Pathfinding or routing

Through a circuit switch

C370S369000

Reexamination Certificate

active

06269097

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a time switching control apparatus and method used in a TDM communication system. More specifically, it relates to an apparatus and method for controlling a 16×16 time switch for switching 512 time slots (i.e., 16 input ports×32) into time slots in any of 16 output ports (channels).
DESCRIPTION OF THE RELATED ART
Generally, a TDM communication system is composed of subscribers wanting to communicate with others, and a time switch connecting the subscribers according to time (by channel) for enabling the communication connection.
A Time Division Multiplexing (TDM) system is a method of transmission by which multiple input signals containing many subscribers' data are multiplexed on a time domain. The system divides data to be transmitted in each channel into Pulse Code Modulation (PCM) data (8 bits) units and transmits them at regular time intervals. The time interval during which each PCM data signal remains in a frame is called a time slot. For example, if n lines are multiplexed, n time slots must exist in a frame. The time slot is referred to as a channel.
The time division multiplexing switch, hereinafter referred to as the time switch, multiplexes many channel signals (time slots) onto a line (communication path) and transmits.
Once multiplexed, it is possible to change the time slot order on the multiplexed frame by using the time switch on the line while dividing the multiplexed signals. Namely, data of a time slot 0 is moved into a time slot 1, and the time slot 1 data is moved into the time slot 0. In this case, the line (port) is also switched as the channel.
Thus, it is possible to achieve communication between subscribers by assigning the time slot 0 and the time slot 1.
The switching of time slots can be carried out by using a buffer memory in the time switch to change the multiplexing order of the multiplexed time slot. This requires a data memory for saving the PCM data of each channel.
Since the addresses that will assign switching based on the line channel number (or number of time slots in one frame) are in the data memory and the control memory, the memory size is “8 bits×n channels” where n is a line channel number (number of time slots).
In order to read the data memory, i.e., in order to read a specific address of the data memory during each time slot, it (the address) is written into a cell (having a specific address) of the control memory in accordance with the order of formation by a control device.
Therefore, when information written in the data memory is read as an output time slot, the information in the data memory address is written by recording the address value in the control memory.
The time switching order (sequence) is performed periodically in each frame until the information in the control memory is changed by the processor.
The time switching currently being used when needed comprises said data memory, control memory, a ROM for suitably converting data to the output status and an attribute memory (RAM) for saving a conversion method and an operation mode about each of the output ports.
The prior art time switching with an 8 bit control memory will be described in detail by referring to the drawings.
FIG. 1
is a block diagram illustrating the operation of an 8 bit control device of a 16×16 control memory currently in use.
The 16×16 time switch comprises:
16 input ports divided into two blocks of respectively 8 ports (0~7 and 8-15);
an 11 bit address input transmitted from the processor in order to control all of the 800H (2
11
)×8 bit sized overall memory;
2 MUXes (
110
)(
115
) for converting the 8 bit serial data transmitted from the upper and lower input ports, respectively, into 8 bit parallel data, and sending the parallel data into the data memory;
a data memory 0 (
120
) composed of 256×8 bit sized DM00 and DM01 for saving said 8 bit parallel data 256 channels (8 ports×32 channels);
a data memory 1 (
125
) composed of 256×8 bit sized DM10 and DM11 for saving said 8 bit parallel data 256 channels (8 ports×32 channels);
a control memory (
150
) composed of a control memory 0 including 256×8 bit sized RAM for controlling said data memory 0 and a control memory 1 including a 256×8 bit sized RAM for controlling said data memory 1 by the subscriber exchange information transmitted by the processor;
a 256×8 bit sized attribute memory (
155
) for controlling each output ports according to the operation mode;
two address MUXes (
160
)(
165
) for choosing between the address transmitted from control memory (
150
) into the data memory (
120
)(
125
), respectively, and the address transmitted from the processor directly into data memory (
120
)(
125
);
a data control block (
170
) controlling the data bus in order to alternatively select and send data transmitted from the processor into control memory (
150
), attribute memory (
155
) and data memory (
120
)(
125
);
two output conversion blocks (
130
)(
135
) for converting data from said data memory (
120
)(
125
), respectively, into the data suitable for output form;
2 DMUXes (
140
)(
145
) for converting each bit of the parallel data from said output conversion blocks (
130
)(
135
), respectively, into serial data by assignment suitable for each output ports; and
16 output ports divided into an 8 bit upper/lower block, respectively.
A clock signal, a frame synchronization signal and a reset signal are inputted into all of said blocks.
FIG. 2
is a block diagram illustrating an overall memory map in the processor of the prior art time switch of FIG.
1
. Since the data memory of the time switch is only written by the primary input ports, the data memory portion is only readable by the processor.
The operation of the time switch will be explained in detail as follows.
If channels are set up and the time switch powers on in a communication system, the serial data is successively input through 16 input ports by synchronizing it with the clock signal. The serial data (each input port×32 channels (time slots) and 0~7 ports, 8~15 ports) is input through 32 channels in a period of one generated frame as synchronized with the frame synchronization signal. The serial signals transmitted through each port are transmitted into the upper/lower port MUX (
110
)/(
115
), respectively, and are converted into 8 bit parallel data for channel division and simplicity of handling.
The parallel data is multiplexed in the MUXes (
110
)(
115
), i.e., input port 0~7 is sent into DM00 (
120
) and DM10 (
125
), and input port 8~15 is sent into DM01 (
120
) and DM11 (
125
), and is stored at the same time. Therefore, the 512 byte sized data memory 0 (
120
) composed of DM00 and DM01, and the 512 byte sized data memory 1 (
125
) composed of DM10 and DM11 respectively store the entire contents of input ports 0~15.
A write address for the data memory (
120
)(
125
) corresponds with the port/channel number of the input port.
FIG. 3
illustrates the 8 bit address format of the data memory.
FIG.
3
(
a
) illustrates the address format of the data memory 00 (DM00) and the data memory 10 (DM10) and FIG.
3
(
b
) illustrates the address format of the data memory 01 (DM01) and the data memory 11 (DM11). The time interval during which data is written on the data memory (
120
)(
125
) is determined by the time slot interval regardless of the processor.
If the time switch circuit is powered on, the processor must write exchange (switching) information into the control memory (
150
) and the attribute memory (
155
) in addition to reading data. This process is the time switch setting process for creating a communication channel. The processor uses the data control block (
170
) in order to choose the memory to write its contents.
When the processor reads/writes the control memory (
150
) or the attribute memory (
155
), or when the processor reads data memory (
120
)(
125
), the processor chooses one among the three kinds of memory by using the upper 3 bits of the 11 bit address bus, an

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