Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-08-09
2010-11-16
Baderman, Scott T (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S020000
Reexamination Certificate
active
07836359
ABSTRACT:
A multi-core microprocessor has a plurality of processor cores which are coupled to a bridge element. The bridge element sends transactions to and/or receives transactions from the processor cores, where each transaction has one or more packets. The transactions include atomic transactions. The bridge element comprises a buffer unit storing a time stamp for each packet sent or received. Furthermore, a multi-core multi-node processor system is provided that has debug hardware to capture and time stamp intra-node and/or inter-node transaction packets. Atomic operations are, for example, atomic read-modify-write instructions.
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Translation of Official Communication in application No. DE 10 2007 009 909.8-53 issued Nov. 21, 2007.
Foster Todd
Lastor Dennis
Singh Padmaraj
Baderman Scott T
Globalfoundries Inc.
Heter Erik A.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Patel Kamini
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