Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2004-07-02
2009-11-17
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07620920
ABSTRACT:
Systems, methods, and other embodiments associated with time separated signals are described. One system embodiment includes a delay circuit, two or more sets of interconnects, and a clocked deracer circuit. In the system embodiment, at least one of the sets of interconnects is arranged as a shield for another set of interconnects. In the system embodiment, the delay circuit may select a timing delay to apply to the first signal to produce the near-end signal based, at least in part, on a desired ratio between a reduction in the slack associated with a setup time on a far-end receiver and a reduction in the slack associated with a hold time on a near-end receiver.
REFERENCES:
patent: 2003/0159118 (2003-08-01), Lindkvist
patent: 2004/0098630 (2004-05-01), Masleid
patent: 2004/0098684 (2004-05-01), Amekawa
patent: 2005/0233573 (2005-10-01), Park
patent: 2005/0246116 (2005-11-01), Foreman et al.
patent: 2006/0192429 (2006-08-01), Broyde et al.
Nettleton Randall J.
Sullivan Thomas J.
Wang Lei
Chiang Jack
Hewlett--Packard Development Company, L.P.
Memula Suresh
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