Electronic digital logic circuitry – Reliability
Patent
1998-07-22
2000-10-17
Tokar, Michael
Electronic digital logic circuitry
Reliability
326 10, 714819, H03K 19003
Patent
active
061337471
ABSTRACT:
The present invention provides an SEU immune solution which minimizes the disadvantages of the increased weight and size of prior art SEU immune circuits. In the present invention, the SEU immune solution can comprise two portions. First, a control portion can be comprised of SEU tolerant electronics as described in the prior art. A processor comprises the second portion and is preferably not SEU immune. The present invention makes it unnecessary for both portions of the circuit to be comprised of SEU tolerant logic in order for the output of the present invention to be SEU tolerant. In particular, the present invention is especially well suited for outer space travel since the present invention will not be upset by SEUs and retains a small package size and light weight.
REFERENCES:
patent: 4162480 (1979-07-01), Berlekamp
patent: 4541067 (1985-09-01), Whitaker
patent: 4587627 (1986-05-01), Omura et al.
patent: 4873688 (1989-10-01), Maki et al.
patent: 5111429 (1992-05-01), Whitaker
patent: 5204841 (1993-04-01), Chappell et al.
patent: 5406513 (1995-04-01), Canaris et al.
patent: 5418473 (1995-05-01), Canaris
patent: 5481555 (1996-01-01), Wade et al.
patent: 5870332 (1999-02-01), Lahey et al.
Advanced Hardware Architecture: AHA 4510 High Speed Reed Solomon Encode/Decoder Data Sheet, 1989.
R. Bose and D. Ray-Chaudhuri, "On a class of Enter Correcting Binary Group Codes,"Inf. and Control, 3, pp. 68-79, 1960.
CCSDS recommendation for Telemetry Channel Coding, CCSDS Secretariat, Communications and Data Systems Division, Code-TS, NASA, 1984.
R. Chein, "Cyclic Decoding Procedures for the Bose-Chaudhuri-Hocquenghem Codes," IEEE Trans. Information Theory, IT-10, pp. 357-363, Oct. 1964.
N. Demassieux, F. Jutand, and M. Muller, "A 10Mhz (255,223) Reed-Solomon Decoder," IEEE 1988 Custom Integrated Circuits Conference, pp. 17.6.1-17.6.4, May 1998.
G. Feng, "A VSLI Architecture for Fast Inversion in GF(2.sup.m)," IEEE Trans. on Computer, vol. 38, No. 10, pp. 1383-1386, Oct. 1989.
T. Fujio, "A Study of High-Definition TV System in the Future," IEee Trans. Broadcast, vol BC-24, No. 4, pp. 347-350, 1983.
A. Hilman and G. Alexanderson, A First Under-Graduate Course in Abstract Algebra, Wadsworth Publishing, pp. 347-350, 1983.
B.A. Laws, Jr. and C.K. Rushforth, "A Cellular-Array Multipler for GF(2.sup.m), " IEEE Trans. on Computers, vol. C-20, pp. 1573-1578, Dec. 1971.
G. Meeker,"High Definition and High Frame Rate Compatible N.T.S.C. Broadcast Television System," IEEE Trans. Broadcast, vol. 34, No. 3, pp. 313-322, Sept. 1988.
B. Mortimer, M. Moore, and Sablatash, "Performance of a Powerful Error-Correcting and Detecting Coding Scheme for the North American Basic Teletext System (NABTS) for Random Indepent Errors: Methods, Equations, Calculations, And Results," IEEE Trans. Broadcast, vol. 36, No. 2, pp. 113-131, Jun. 1990.
I. Reed and G. Solomon, "Polynomial Codes over Certain Finite Fields,"J. Soc. Industrial Applied Mathematics, vol. 8, No. 2, pp. 300-304, Jun. 1996.
H. Shao and I. Reed, "on the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays," IEEE Transactions on Computers, vol. 37, No. 10, pp. 1273-1280, Oct. 1988.
Y. Sugiyama, M. Kasahara, S. Hirasawa, and T. Namekawa, "A Method for Solving Key Equation for Decoding Goppa Codes," Inf. Control, 27, pp. 87-99, 1975.
C. Wang, T. Troung, H. Shao, L. Deutsch, and J. Omura, "VSLI Architectures for Computing Multiplications and Inverses in GF(2.sup.m)," IEEE Transactions on Computers, vol. C-34, No. 8, pp. 709-717, Aug. 1985.
S. Whitaker, J. Canaris, and P. Owlsey, "Custom CMOS Reed-Solomon Coder for the Hubble Space Telescope," Proceedings of the IEEE Military Communications Conference, Monterey, CA, pp. 4.3.1-4.3.5, Oct. 1990.
S. Whitaker, J. Canaris, and K. Cameron, "Reed-Solomon VSLI Code for Advanced Television", IEEE Transactions on Circuits and Systems for Video Technology, pp. 1-21, Jun. 1991.
C. Yeh, I. Reed, T. Troung, "Systolic Multipliers for Finite Fields GF(2.sup.m)", IEEE Transactions on Computers, vol. C-33, pp. 357-360, Apr. 1984.
Digital Spectrum Compatible, Technical Descripition, Zenith Electronic Corporation and AT&T, Feb. 22, 1991.
K. Niwa, T. Araseki, T. Nishitani, "Digital Signal Processing for Video," IEEE Circuits and Devices Magazine, vol. 6, No. 1, pp. 27-32, Jan. 1990.
H. Cha, E. Rudnick, J. Patel, R. Iyer and G. Choi," A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults," IEEE Transactions on Computers, vol. 45, No. 11, pp. 1248-1256, Nov. 1996.
J.F. Leavy, L. F. Hoffmann, R.W. Shovan and M. T. Johnson, "Upset Due To A Single Particle Caused Propagated Transient In A Bulk CMOS Microprocessor," IEEE Transactions on Nuclear Science, vol. 38, No. 6, pp. 1493-1499, Dec. 1991.
R. Schneiderwind, D. Krening, S. Buchner, K. Kang and T. R. Weatherford, "Laser Confirmation of SEU Experiments in GaAs MESFET Combinational Logic" IEEE Transactions on Nuclear Science, vol. 39, No. 6, pp. 1665-1670, Dec. 1992.
R. A. Reed, M. A. Carts, P. W. Marshall, C. J. Marshall, S. Buchner, M. La Macchia, B. Mathes and D. McMorrow, "Single Event Upset Cross Sections At Various Data Rates," IEEE Transactions on Nuclear Science, vol. 43, No. 6, pp. 2862-2867, Dec. 1996.
S. Buchner, M. Baze, D. Brown, D. McMorrow and J. Melinger, "Comparison of Error Rates in Combinational and Sequential Logic, " IEEE Transactions Nuclear Science, vol. 44, No. 6, pp. 2209-2216, Dec. 1997.
P.E. Dodd, F. W. Sexton, M.R. Shaneyfelt, B. L. Draper A. J. Farino and R. S. Flores, "Impact of Technology Trends on SEU in CMOS SRAMS," IEEE Transactions on Nuclear Science, vol. 43, No. 6 pp. 2797-2804, Dec. 1996.
S. Whitaker, J. Canaris and K. Liu, "SEU Hardened Memory Cells For A CCSDS Reed Solomon Encoder," IEEE Transactions on Nuclear Science, vol. 38, No. 6, pp. 1471-1477, Dec. 1991.
M. N. Liu and S. Whitaker, "Low Power SEU Immune CMOS Memory Circuits," IEEE Transactions on Nuclear Science, vol. 39, No. 6, pp. 1679-1684, Dec. 1992.
J. Canaris and S, Whitaker, "Circuits Techniques for the Radiation Environment of Space," IEEE 1995 Customer Intergrated Circuits Conference, pp. 77-80, 1995.
J. Gambles and G. Maki, "RAD-Tolernat Flight VLSI From Commerical Foundries,"Proceedings of the 39th Midwest Symposium on Circuits and Systems, pp. 1227-1230, Aug. 18-21, 1996.
F. W. Sexton et al., "SEU Simulation and Testing of Resistor-Hardened D-Latches in the SA3300 Microprocessor, "IEEE Transactions on Nuclear Science, vol. 38, No. 6, pp. 1521-1528, Dec. 1991.
Y. Savaria, N. Rumin, J. Hayes and V. Agarwal, "Soft-Error Filtering: A Solution to the Reliablity Problem of Future VLSI Digital Circuits," Proceeding of the IEEE , vol. 74, No. 5, pp. 669-683, 1986.
M. P. Baze and S. P. Buchner, "Attentnuation of Single Event Induced Pulses in CMOS Combination Logic," IEEE Transaction on Nuclear Science, vol. 44, No. 6, pp. 2217-2222, Dec. 1997.
P. Liden, P. Dahlgren, R. Johansson and J. Karlsson, "On Latching Probability of Particle Induced Transients in Combinational Networks," IEEE Computer Society Press, 24th International Symposium on Fault-Tolerant Computing, pp. 340-349, Jun. 15-17, 1994.
K. J. Haas and J. W. Gambles, "Single Event Transients in Deep Submicron CMOS,"42nd Midwest Symposium on Circuits and Systems, Aug. 1999.
K. Joe Haas, Jody Gambles, Bill walker and Mike Zampaglione, "Mitigating Single Event Upstes From Combinational Logic," 7th NASA Symposium on VLSI Design, pp. 4.1.1-4.1.10, 1998.
S.M. Kang and D. Chu, "CMOS Circuit Design for Prevention of Single Event Upset," International Conference on Computer Design, 1986.
T. Ma and P. Dressendorfer, Ionizing Radiation Effects in CMOS Devices and Circuits, Chapter 9, pp. 484-576, 1989.
Tokar Michael
Tran Anh
University of New Mexico
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