Time multiplexing a plurality of configuration settings of a pro

Details Time multiplexing a plurality of configuration settings of a pro Time multiplexing a plurality of configuration settings of a pro

1996-01-17

1998-06-02

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 40, H03K 19173, H03K 738

Patent

active

057606021

ABSTRACT:
A field programmable gate array (FPGA) system for time multiplexing a plurality of programmable configurations of the FPGA. The system includes a plurality of configuration memory cells which are loaded with configuration information. A time slice selector couples selected configuration memory cells to programmable switch elements that determine the configuration and function of the logic within the FPGA. A time slice controller determines which of the configuration memory cells the time slice selector couples to the programmable switch elements. The configuration memory cells may be implemented with half SRAM cells and the time slice selector may be implemented with P-channel transistors.

REFERENCES:
patent: 3987286 (1976-10-01), Muehldorf
patent: 4134150 (1979-01-01), Shiga
patent: 4623989 (1986-11-01), Blake
patent: 5214327 (1993-05-01), Saeki et al.
patent: 5426378 (1995-06-01), Ong
patent: 5444393 (1995-08-01), Yoshimori et al.

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