Time multiplexed addressing circuitry

Details Time multiplexed addressing circuitry Time multiplexed addressing circuitry

1996-06-06

1998-04-28

Saras, Steven

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

345100, 345205, G09G 334

Patent

active

057450889

ABSTRACT:
An array of individual elements (10) having reduced control circuitry as compared to existing devices. Sets of elements (11) share a memory cell (12), such that each memory cell (12) has the same fanout as other memory cells (12). Each element (11) in a set is switched to an on or off state via a reset line (13) that is separate from that of the other elements (11) in that set. Data is loaded in split bit-frames during a set time period, such that each split bit-frame contains only the data for elements (11) on one reset line (13). Thus, the same memory cell (12) can be used to deliver data to all elements (11) in its fanout because only one element (11) in the fanout is switched at a time.

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