Time interval measurement system incorporating a linear ramp...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Generating sawtooth or triangular output

Reexamination Certificate

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Details

C327S095000

Reexamination Certificate

active

06194925

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a linear ramp generating and control circuit and in particular, to such a circuit which may be digitally controlled by and for use in association with a time measurement apparatus.
BACKGROUND OF THE INVENTION
The linear ramp generating and control circuit of the present invention finds particular applicability in a measurement apparatus for measuring time intervals between signal events, wherein each measured interval comprises the summation of a coarse clock count and fine or calibrated vernier counts of the measured fractional clock periods after each START and STOP event. Such a time measurement system is disclosed in U.S. Pat. No. 4,908,784 to Box, the entirety of which is herein incorporated by reference. More specifically, the linear ramp circuit of the present invention is an improvement of the linear ramp circuit of the Box '784 device as disclosed in FIGS. 9
e-f
and accompanying specification. As such, the present invention concerns that portion of the total time measurement apparatus necessary to generate both a rough clock count (course count) and an uncalibrated vernier count (fine count) when provided with START and STOP signals.
As discussed in the Box '784 patent, measurement of calibrated vernier counts of the clock periods or fractional beginning and end times of any event is effectuated with a voltage address developed by associated start and stop ramp capacitive circuitry and passed to an analog to digital converter which is used to access the stored corresponding time value from a calibrated fine count memory. Recharging of the hold capacitor in the Box '784 device was effectuated through a diode clamp network to restore the baseline voltage to the hold capacitor during the recovery mode of operation. Limitations of the diode clamp circuit include relatively poor consistency and lack of repeatability between successive data samples, relatively long time constants of the hold capacitor voltage recovery (requiring increased time interval between data samples to ensure stable voltage levels), and poor thermal dependence (thermal drift).
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a linear ramp generation circuit which decreases errors such as drift, signal noise, and baseline voltage instability.
According to the present invention, there is provided a linear ramp generation circuit adapted to operate sequentially in three modes: a discharge mode when the voltage on a hold capacitor is linearly discharged; a hold mode when the voltage on the hold capacitor is output to an analog-to-digital converter; and a recovery mode when the voltage on the hold capacitor returns to its baseline level prior to the successive measurement cycle. Upon occurrence of a measured signal event, whether a START or STOP event, the circuit of the present invention operatively couples a regulated current sink to the associated hold capacitor in the START/STOP track and hold circuits (data sample or discharge mode). This initiates a linear discharge of the hold capacitor from a base level to a data level, the data level being determined by the time interval that the current sink network is coupled to the hold capacitor. During the hold mode of operation, the data level (capacitor voltage) is subsequently passed to the analog to digital converter and used to calculate the fine count time periods. In turn, the hold capacitor is recharged prior to the next signal event during the recovery phase by an active feedback amplifier network. Discharge of the precision hold capacitors by the regulated current sink network during the discharge or data sample phase of the circuit operation results in a substantially linear discharge of the hold capacitor, the full range of which is defined through calibration to coincide with one master clock cycle period.
One of the linear ramp generator circuits of the present invention is provided for each START and STOP fine count measurement subsystem of the time interval measurement device. Control signals are provided to the START and STOP linear ramp generator circuits of the measurement device, and include SRC (source) and SNK (sink) and their complementary signals. The control signals can be derived directly from the START and STOP event signals and an asynchronous master clock.
In summary, the major operational components of the ramp generator circuit include a SRC (source) control switching network, a SNK (sink) control switching network, a stable current sink network, and an active feedback network for efficient recovery mode operation. The SRC control switching network controls the hold capacitor recharge during the recovery mode of operation by operatively connecting the active feedback network to the hold capacitor. The SRC control switching network includes a differential configured current-steering switch, which may be a pair of emitter-coupled n-p-n type bipolar transistors and associated resistor network. The SNK network controls the discharge of the hold capacitor by coupling and un-coupling the current sink to the hold capacitor during the discharge mode of operation. The SNK network includes a differential current-steering network, which may be a emitter-coupled pair of n-p-n transistors and associated resistor and capacitor network. The constant current sink network is implemented to linearly discharge the hold capacitor during the discharge mode operation. The constant current network includes a base-coupled n-p-n transistor, the base node of transistor being coupled to the output of an op-amp and an associated impedance network. The ramp generator circuit also includes an active feedback network which is operatively connected by the SRC control switching network to the hold capacitor during the recovery mode of circuit operation to recharge the hold capacitor to its baseline voltage. Desirably, the active feedback circuit recharges the hold capacitor through a substantially second-order or near “Bessel”—type response.
Additional objects and advantages of the invention will be set forth in the detailed description which follows when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 4301360 (1981-11-01), Blair
patent: 4302689 (1981-11-01), Brodie
patent: 4323796 (1982-04-01), Lathrope
patent: 4393318 (1983-07-01), Takahashi et al.
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patent: 4634993 (1987-01-01), Koen
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patent: 4908784 (1990-03-01), Box et al.
patent: 4962325 (1990-10-01), Miller et al.
patent: 4982350 (1991-01-01), Perna et al.
patent: 5162670 (1992-11-01), Itakura et al.
patent: 5341037 (1994-08-01), Miki et al.
patent: 5343089 (1994-08-01), Itakura et al.
patent: 5352933 (1994-10-01), Kogan
patent: 5825218 (1998-10-01), Colli et al.

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