Time interpolating direct digital synthesizer

Details Time interpolating direct digital synthesizer Time interpolating direct digital synthesizer

2000-06-02

2002-03-05

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C708S271000, C327S107000

Reexamination Certificate

active

06353649

ABSTRACT:

TECHNICAL FIELD
This invention relates in general to synthesizers, and more particularly to a time interpolating direct digital synthesizer.
BACKGROUND
In a direct digital synthesizer based on digital phase or time correction, such as that shown in
FIG. 2
, a digital numeric multiplier is typically required. The multiplier is undesirable, especially in portable radio applications, as it dissipates a large fraction of the total power used by the synthesizer. Current best implementations of such a multiplier approach show the multiplier consuming about 40% of the total synthesizer power at maximum output frequency. A need thus exists for a simplified synthesizer that does not need a multiplier, while maintaining full functionality.


REFERENCES:
patent: 4933890 (1990-06-01), Nuytkens et al.
patent: 4951237 (1990-08-01), Essenwanger
patent: 5053982 (1991-10-01), McCune, Jr.
patent: 5247469 (1993-09-01), McCune, Jr.
patent: 5469479 (1995-11-01), Chang et al.
patent: 5905388 (1999-05-01), Valk et al.
Nosaka, H., Nakagawa, T., and Yamagishi A., “A Phase Interpolation Direct Digital Synthesizer with a Digitally Controlled Delay Generator,” 1997 Symposium on VLSI Circuits, Digest of Technical Papers No. 4-930813-76-X, pp. 75-76.

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