Time domain bridging circuitry for use in determining output...

Details Time domain bridging circuitry for use in determining output... Time domain bridging circuitry for use in determining output...

2007-09-18

2007-09-18

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S193000, C365S194000, C365S233100, C365S230080

Reexamination Certificate

active

11177540

ABSTRACT:
A method and circuitry for alleviating the adverse effect of variable read decode propagation delays and variable output circuitry propagation delays on the read latency, and specifically for generating output enable signals at an appropriate time in light of such variable delays, is disclosed. In one embodiment, a first time domain as specified by an internal clock is delayed by the propagation delay of the read decoder block plus the propagation delay of the output circuitry via a model to create a second time domain which lags the first time domain. Processing in the second time domain associates the internal read command with a particular external clock cycle, and accounts for the specified read latency of the device. The output of such second time domain processing is a signal indicative of which external cycle should be used to enable the outputs. This signal is then converted back into the first timing domain by latches which lead the second timing domain.

REFERENCES:
patent: 6687185 (2004-02-01), Keeth et al.
patent: 6762974 (2004-07-01), Johnson et al.
patent: 7065001 (2006-06-01), Johnson et al.
patent: 2005/0128828 (2005-06-01), Lee
Sang-Bo Lee et al., “A 1.6 Gb/s/pin Double-Data-Rate SDRAM With Wave-Pipelines CAS Latency Control,” 2004 IEEE Int'l Solid State Conference § 11.6 (Feb. 17, 2004).
U.S. Appl. No. 10/910,838, filed Aug. 4, 2004, Johnson et al.

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