Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2010-03-04
2011-10-11
Cleary, Thomas J (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S118000
Reexamination Certificate
active
08037226
ABSTRACT:
A system, apparatus and method for making possible more efficient utilization of available band-width on the system's bus connection between, from and/or to modules incorporated in the system and/or reduction of accuracy requirements for clock functions utilized in the system. The system comprises at least one of a plurality of modules that further comprise at least one actual clock. The at least one module further comprises a scheduler coupled to the at least one clock, wherein the scheduler is configured to receive a virtual schedule comprising a time slot for sending a message to the communication bus. The scheduler is further configured to determine an actual time for sending a message in relation to the virtual schedule and according to time kept in the at least one actual clock. The module is configured to send a message according to the actual time, wherein the module starts transmission of the message according to the actual time. By sending the module at the actual time, the message begins within an adjacent time slot on the communication bus.
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Brundidge & Stanger, P.C.
Cleary Thomas J
Xinshu Management, L.L.C.
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