Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1996-01-25
1998-06-16
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
36518904, H04L 2536
Patent
active
057683255
ABSTRACT:
A delay circuit externally adjustable for the delay time "n" as desired, which comprises a FIFO (FIRST-IN, FIRST-OUT) type memory, a self-load counter, and a decoder circuit. In addition to a data signal, an input clock is inputted to the memory as the write clock and the read clock. The self-load counter operates in synchronization with the input clock, and loads a setting of a load value-designating signal at a prescribed number of counts. The decoder circuit receives the output of the self-load counter which has a prescribed cycle, and outputs a reset signal with the same cycle to the memory. This cycle determines the delay time. The delay circuit allows a greatly reduced number of ICs used as compared with the prior art, even for increased delay times.
REFERENCES:
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MOS Integrated Circuit (.mu.PD42101), High-Speed Line Buffer for NTSC TV, NEC Corporation, 1989.
Sato Shinji
Yamamoto Rieko
Chin Stephen
Deppe Betsy L.
NEC Corporation
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