Time-adjustable delay circuit

Details Time-adjustable delay circuit Time-adjustable delay circuit

1996-01-25

1998-06-16

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

36518904, H04L 2536

Patent

active

057683255

ABSTRACT:
A delay circuit externally adjustable for the delay time "n" as desired, which comprises a FIFO (FIRST-IN, FIRST-OUT) type memory, a self-load counter, and a decoder circuit. In addition to a data signal, an input clock is inputted to the memory as the write clock and the read clock. The self-load counter operates in synchronization with the input clock, and loads a setting of a load value-designating signal at a prescribed number of counts. The decoder circuit receives the output of the self-load counter which has a prescribed cycle, and outputs a reset signal with the same cycle to the memory. This cycle determines the delay time. The delay circuit allows a greatly reduced number of ICs used as compared with the prior art, even for increased delay times.

REFERENCES:
patent: 4506348 (1985-03-01), Miller et al.
patent: 4740924 (1988-04-01), Tielert
patent: 4876670 (1989-10-01), Nakabayashi et al.
patent: 4953128 (1990-08-01), Kawai et al.
patent: 4961169 (1990-10-01), Matsumura et al.
patent: 5073733 (1991-12-01), Tanno et al.
patent: 5406518 (1995-04-01), Sun et al.
MOS Integrated Circuit (.mu.PD42101), High-Speed Line Buffer for NTSC TV, NEC Corporation, 1989.

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