Tileable field-programmable gate array architecture

Electronic digital logic circuitry – Multifunctional or programmable – Array

Reexamination Certificate

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Details

C326S038000, C326S039000

Reexamination Certificate

active

07342416

ABSTRACT:
An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

REFERENCES:
patent: 5469003 (1995-11-01), Kean
patent: 5483178 (1996-01-01), Costello et al.
patent: 5485103 (1996-01-01), Pedersen et al.
patent: 5491353 (1996-02-01), Kean
patent: 5504439 (1996-04-01), Tavana
patent: 5521529 (1996-05-01), Agrawal et al.
patent: 5528176 (1996-06-01), Kean
patent: 5537057 (1996-07-01), Leong et al.
patent: 5541530 (1996-07-01), Cliff et al.
patent: 5570041 (1996-10-01), El Avat et al.
patent: 5598109 (1997-01-01), Leong et al.
patent: 5606266 (1997-02-01), Pedersen
patent: 5606267 (1997-02-01), El Ayat et al.
patent: 5614840 (1997-03-01), McClintock et al.
patent: 5617042 (1997-04-01), Agrawal
patent: 5621650 (1997-04-01), Agrawal et al.
patent: 5644496 (1997-07-01), Agrawal et al.
patent: 5668771 (1997-09-01), Cliff et al.
patent: 5671432 (1997-09-01), Bertolet et al.
patent: 5682107 (1997-10-01), Tavana et al.
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5761099 (1998-06-01), Pedersen
patent: 5764583 (1998-06-01), Cliff et al.
patent: 5809281 (1998-09-01), Steele et al.
patent: 5815003 (1998-09-01), Pedersen
patent: 5825202 (1998-10-01), Tavana et al.
patent: 5828229 (1998-10-01), Cliff et al.
patent: 5874834 (1999-02-01), New
patent: 5878051 (1999-03-01), Sharma et al.
patent: 5880598 (1999-03-01), Duong
patent: 5977793 (1999-11-01), Reddy et al.
patent: 5990702 (1999-11-01), Agrawal et al.
patent: 6020755 (2000-02-01), Andrews et al.
patent: 6034544 (2000-03-01), Agrawal et al.
patent: 6064225 (2000-05-01), Andrews et al.
patent: 6084427 (2000-07-01), Lee et al.
patent: 6084429 (2000-07-01), Trimberger
patent: 6091263 (2000-07-01), New et al.
patent: 6108806 (2000-08-01), Abramovici et al.
patent: 6181162 (2001-01-01), Lytle et al.
patent: 6211697 (2001-04-01), Lien et al.
patent: 6301696 (2001-10-01), Lien et al.
patent: 6446242 (2002-09-01), Lien et al.
patent: 6463560 (2002-10-01), Bhawmik et al.
patent: 6476636 (2002-11-01), Lien et al.
patent: 6550030 (2003-04-01), Abramovici et al.
patent: 6611153 (2003-08-01), Lien et al.
patent: 6631487 (2003-10-01), Abramovici et al.
patent: 6651238 (2003-11-01), Wells et al.
patent: 6681354 (2004-01-01), Gupta
patent: 6700404 (2004-03-01), Feng et al.
patent: 6725442 (2004-04-01), Cote et al.
patent: 6870396 (2005-03-01), Lien et al.
patent: 6888375 (2005-05-01), Feng et al.
patent: 7015719 (2006-03-01), Feng et al.
patent: 7157938 (2007-01-01), Feng et al.
patent: 0 415 542 (1991-03-01), None
patent: 0 415 542 (1991-03-01), None
patent: 2 346 240 (2000-08-01), None
“VariCore™ Embedded Programmable Gate Array Core (EPGA™) 0.18 μm Family,” Actel Corp. Data Sheet, 15 pages, Dec. 2001.
“Welcome to VariCore's website,” [Internet] http://www.actel.com/varicore/index3.html first visited in Feb. 2001, printed Jul. 3, 2003, Actel Corp., 1 page.
“Overview,” [Internet] http://actel.com/varicore/about.index.html, first visited in Feb. 2001, printed Jul. 3, 2003, Actel Corp., 3 pages.
“Products-VariCore,” [Internet] http://actel.com/varicore/products/index.html, first visited in Feb. 2001, printed Jul. 3, 2003, Actel Corp., 2 pages.
“Documentation,” [Internet] http://actel.com/varicore/support/index.html first visited in Feb. 2001, printed Jul. 3, 2003, Actel Corp., 1 page.
“Design Alliance,” [Internet] http://actel.com/varicore/alliances/index.html, first visited in Feb. 2001, printed Jul. 3, 2003, Actel Corp., 1 page.
“Press Releases,” [Internet] http://actel.com/varicore/press/index.html, first visited in Feb. 2001, printed Jul. 3, 2003, Actel Corp., 1 page.
“Contact Info”, [Internet] http://actel.com/varicore/contact/index.html, first visited in Feb. 2001, printed Jul. 3, 2003, Actel Corp., 1 page.
“Market & General FAQ,” [Internet] http://actel.com/varicore/about/FAQs.html, first visited in Feb. 2001, printed Jul. 3, 2003, Actel Corp. 3 pages.
Bryant, I et al., “The Actel Embeddable FPGA Core,” Internet published at http://www.actel.com/varicore/support//index.html first visited in Feb. 2001, printed Jul. 5, 2003.
Gibson, G. et al., “Boundary Scan Access of Built-In Self-Test for Field Programmable Gate Arrays”, ASIC Conference and Exhibit Proceedings Tenth Annual IEEE International, Portland, Oregon, USA, pp. 57-61, Sep. 7-10, 1997.
Krupnova, H., “Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs”, Design Automation and Test in Europe Conference and Exhibition Proceedings, Munich, Germany, pp. 587-594, Mar. 9-12, 1999.
Hamilton, C., “Methods for Boundary Scan Access of Built-In Self-Test for Field Programmable Gate Arrays”, Southeastern Proceedings IEEE, Lexington, Kentucky, USA, pp. 210-216, Mar. 25-28, 1999.
Xu, M. et al., “Layout-Driven High Level Synthesis for FPGA Based Architectures”, Design, Automation and Test in Europe Proceedings, Paris, France, pp. 446-450, Feb. 23-26, 1998.

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