Tie-high and tie-low circuit

Details Tie-high and tie-low circuit Tie-high and tie-low circuit

2007-05-22

2007-05-22

Le, Don (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S082000

Reexamination Certificate

active

11064362

ABSTRACT:
A tie-high, tie-low circuit having a tie-high output and a tie-low output comprises a regenerative device to be coupled with both the tie-high and the tie-low outputs, and at least a PMOS device and a NMOS device to be coupled respectively with a high voltage and a low voltage. A diode, a NMOS device, and a PMOS device are used as regenerative devices in three examples. These three examples exhibit improved electrostatic discharge (ESD) tolerance.

REFERENCES:
patent: 5900742 (1999-05-01), Kolze et al.
patent: 6396306 (2002-05-01), Dring et al.
patent: 2006/0092592 (2006-05-01), Huang

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