Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2000-01-15
2003-04-29
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S061000, C710S020000, C710S200000, C710S264000
Reexamination Certificate
active
06557051
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to enhancing Read and Write operations of an integrated circuit serial interface.
2. Description of the Related Art
Data transfer at a serial port or interface, using Read and Write commands, is relatively slow, because each byte is read or written bit-by-bit in single file. No use is made of the possibility of reading and/or writing data simultaneously, or taking advantage of other situations consistent with the constraints imposed by use of a serial interface.
What is needed is an approach that allows an increase in the effective rate of performance of Read and Write operations at a serial interface. Preferably, the approach should allow for an increased rate of operation where the operation involves two consecutive Read commands or a Read command followed by a Write command and should allow data transfer rate improvement where the Read commands are continuous and where the Read commands interrupt each other.
SUMMARY OF THE INVENTION
These needs are met by the invention, which uses an input serial interface and an output serial interface, whose operations are synchronized, to perform certain operations in tandem and to thus achieve some of the benefits of a parallel port or interface. In a first embodiment, a Read command is performed on one communication channel and a subsequent Write command that is received is performed synchronously on another communication channel.
In another embodiment, a first Read command is received on a first communication channel, followed by a sequence of K NOP (no operation) commands, where 0 K<N−1 and N is the number of data units (bytes, nibbles or other fixed length consecutive sequences of data bits, referred to collectively herein as “data units”) used to represent a data word, followed immediately by a second Read command. This sequence of commands will interrupt the performance of the first Read command after K+1 data units of the first word are read on a second communication channel and will begin reading the first data unit of the second word on the second channel. This truncation of a Read command, before all data units of a word have been Read is especially useful where the word to be read is a control or supervisory word for which all data units need not be read. Reading of the first word can be terminated after K+1 data units have been read, thus allowing a portion of another command to be executed in the time slot(s) that would have been used to read the remaining N−K−1 data units of the first word.
In another embodiment, a first Read command received on a first communication channel, followed by a sequence of N−1 NOP commands, followed by a second Read command, will cause the first Read operation to be performed on all N data units of the first word before at least one data unit of the second word is read, as part of a continuous read operation, in a pattern in which no time slot is unused.
REFERENCES:
patent: 4873671 (1989-10-01), Kowshik et al.
patent: 5369618 (1994-11-01), Takasugi
patent: 5815456 (1998-09-01), Rao
patent: 6032204 (2000-02-01), Huff et al.
Cirrus Logic Inc.
Elamin Abdelmoniem
Gaffin Jeffrey
Lin, Esq. Steven
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