Through-the-substrate investigation of flip-chip IC's

Details Through-the-substrate investigation of flip-chip IC's Through-the-substrate investigation of flip-chip IC's

2001-02-10

2003-02-11

Anderson, Bruce (Department: 2881)

Radiant energy

Inspection of solids or liquids by charged particles

Methods

C250S309000, C250S491100, C250S492210

Reexamination Certificate

active

06518571

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods and apparatus for exposing conductors of an IC (integrated circuit) device through the substrate to aid in debug and/or failure analysis.
2. The Prior Art
Exposing conductors of an IC device for failure analysis, debug, and even repair, has become commonplace. Typically, a FIB (focused ion beam) is used to mill away material to expose the conductor, sometimes with the introduction of a halogen-containing compound to enhance the milling rate. Conductors are cut and conductive material is deposited, to effect circuit modifications or to construct probe pads. The IC device is stimulated to produce signals on the exposed conductors and probe pads, and these signals are detected using the FIB as a probe or using an electron-beam probe or mechanical probe.
Navigation tools are available to assist in locating the conductor portion to be exposed. For example, a FIB system commercially available as the “IDS P2X” (Probe Point eXtension) system from Schlumberger Technologies, Inc., San Jose, Calif., provides software-based navigation tools in which the CAD layout and live FIB images of the device can be registered to one another. Once registered, these images are linked so that when the user selects a point or feature on one of the images the corresponding location is identified on the other image. For example, a buried conductor which is not visible on the FIB image can be identified on the CAD layout image in order to position a “FIB operation box” which defines an area where the FIB is to be scanned for milling. FIB milling in this area exposes precisely the portion of the conductor of interest, without damage to surrounding structure of the IC device. Selective gas-enhanced milling and suitable end-point detection allow the milling to be stopped before damaging the exposed conductor portion.
Such processes have heretofore generally been carried out from the “front side” of the device from the side of the substrate on which the layers defining the circuit are fabricated. An initial FIB image of the front side of the device contains information about the location of device structure which is used to register the FIB image to the stored layout data from which the CAD image is prepared. For example, bond pads or fiducial marks visible on the front side of the device indicate the registration of the top device layer. Since the buried device layers are aligned with the top device layer within some margin of offset error, features visible on the top layer are used for registration.
Navigation techniques are also known in which one image of the device, such as an optical image or SEM (scanning electron microscope) image, is used as an overlay on a SIM (scanning ion microscope) image of the device to assist in directing a FIB to expose a buried feature. See, for example, U.S. Pat. No. 4,683,378 to Shimase el al. When there is not enough unique surface information near the FIB operation area to align the images, the imaging area of the FIB can be deflected to permit alignment over a much larger area, while maintaining the needed resolution and accuracy. See U.S. Pat. No. 5,401,972 to Talbot el al. Yet another approach is to use a high-accuracy stage to navigate the FIB from fiducial information on the metal layer of the device. Such stages are costly, requiring a laser interferometer for determining position, and accuracy is limited by thermal mechanical drift and FIB drift.
Such techniques are suitable for devices which-are accessible from the front side, such as those designed for conventional packaging of the type having bond pads around the periphery and having the central portion of the device unobstructed by contacts or package leads. However, increased device operating speeds demand lower impedances and thus shorter connections-from active elements of the device to the package leads. At the same time, larger and more complex devices call for an increased number of input/output connections, resulting in unacceptably large die and packages. A response to these needs has been the development of so-called “flip-chip” (“C4”) packaging in which the bond connections are arrayed over the entire front side of the IC device and these align with a corresponding array of bond connections on the package. Solder “bumps” electrically connect the bond connections of the device with those of the package. The connection length and impedance from active element to package pin are reduced, and the number of connections per unit area of device and package are increased, relative to the peripheral-connection arrangements of the past.
A disadvantage of the “flip-chip” packaging arrangement is that the top layer of the device is covered with an array of bond pads, making access to buried conductors difficult or impossible even with unpackaged devices. For packaged devices, the package covers the entire front side of the device so that there can be no chance of accessing buried conductors from the front side. Improved techniques are needed for debug of such devices.
Another consequence of increasingly complex devices is the need to reduce line widths and increase the number of layers. “Flip-chip” devices now in fabrication are using 0.35 &mgr;m design rules, with still more advanced design rules of 0.20 &mgr;m and below expected before long. As line widths decrease and the number of layers increases, layer-to-layer registration becomes more of a problem. CAD layout data shows the ideal layer-to-layer registration, but the fabricated devices will have some misregistration. The more layers involved, the greater the cumulative registration error (“stack-up” error). Smaller design rules and stack-up error together increase the chance of missing a conductor of interest or of inadvertently damaging the device when conducting FIB operations.
Techniques are known for failure-analysis investigation of IC devices through the substrate, from the “back side,” though none has adequately addressed the need for debug of “flip-chip” devices. One approach is to acquire IR (infrared) optical microscope images through the silicon substrate, given that silicon is transparent at wavelengths in the range of about 0.9 &mgr;m to about 1.9 &mgr;m. See, for example, J. BROWN,
Failure analysis of plastic encapsulated components—the advantages of IR microscopy,
J. Microscopy, Vol. 148, Pt. November 2, 1987, pp. 179-194.
Failure analysis on “flip-chip” devices typically starts with software simulation and external testing to localize the failure. An IR laser can then be shined through the back side of the device to inject light into the active region of a transistor of interest. If the transistor was already on, there is no change. If the transistor was off, the IR beam induces a leakage current which may be detected on the external pins of the device. This OBIC (“optical beam-induced current) technique permits logic analysis, but does not give any timing information.
An electro-optic probing technique is also known in which an IR laser is pulsed and the change of propagation delay is measured as a function of carrier density. This technique gives a direct measure of how quickly the transistor is switching and of its state. While effective for bipolar devices, it does not work well with CMOS devices due to low carrier density change. This makes it unsuitable for the long duty-cycle measurements needed for microprocessor debug.
A destructive technique suitable only for failure analysis is to delaminate the device layer by layer. Rather than performing a functional analysis, the structure is examined for functionality of individual cells or elements of a cell. By testing and simulation it is often possible to pre-localize the fault to some 10 or 100 or 1000 nets, and then examine whether the nets connect together as they should. If an open via or non-functional transistor is found, then the problem may have been identified. This technique is not suitable for debug, as it does not allow detection of signals on the nets as the device is operated,

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