Abrading – Abrading process – Abradant supplying
Reexamination Certificate
2002-09-30
2004-03-16
Nguyen, George (Department: 3723)
Abrading
Abrading process
Abradant supplying
C451S036000, C451S041000, C451S285000, C451S921000, C451S526000, C051S297000
Reexamination Certificate
active
06705928
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit (IC) manufacturing, and more specifically, to an apparatus for and a method of delivering a slurry through a pad for chemical-mechanical polish (CMP).
2. Discussion of Related Art
A transistor on a chip is usually fabricated from semiconductor material, such as Silicon, and electrically insulating material, such as Silicon Oxide and Silicon Nitride. The transistor is subsequently wired up with electrically conducting material, such as doped polysilicon and metal. The electrically conducting material may be stacked in multiple layers that are separated by electrically insulating material.
In order to improve device density, both the transistor in the front-end of semiconductor processing and the wiring in the back-end of semiconductor processing must be scaled down. The scaling of the transistor and the scaling of the wiring must be carefully balanced in order to prevent degrading performance or reliability.
In 1965, Gordon Moore first observed that the number of transistors per unit area on a chip appeared to double approximately every 18 months. Ever since then, the semiconductor industry has managed to deliver the improvement in device density projected by the so-called Moore's Law.
Maintaining the schedule over the ensuing decades has traditionally required continual enhancements to the processes of photolithography and etch to reduce the critical dimensions (CDs) that can be successfully patterned in the features across the chip. In addition, significant improvements had to be made to the processes of ion implantation, thermal processing, and deposition to produce the desired doping levels and film thicknesses across the chip.
Photolithography was able to keep up with the requisite reductions in CD for each succeeding device generation or technology node. However, improving the resolution for photolithography often required sacrificing the depth of focus (DOF). A shrinking DOF must be counteracted by a reduction in the topography, or surface relief, that inevitably accompanied the processes of etch and deposition. Thus, reduction in topography, or planarization, became necessary for both the front-end and the back-end of semiconductor processing for the most advanced devices.
Chemical-mechanical polish (CMP) is an enabling technology for performing planarization. The process of CMP combines mechanical abrasion and chemical dissolution. Abrasion involves a pad, in conjunction with a slurry of abrasive particles, that flattens and smoothens the relief on a surface. Dissolution involves chemicals in the slurry which react with certain materials at the surface to form soluble byproducts that may be removed.
Successful planarization requires fresh slurry to be properly distributed to, and old slurry to be properly removed from, the interface between an upper surface of the pad and the surface that is being polished. With the transition from 200-millimeter (mm) diameter wafers to 300-mm diameter wafers, the control of polish rate, polish uniformity, and polish selectivity has become ever more dependent on the proper distribution of slurry between the upper surface of the polish pad and the surface that is being polished.
A dual Damascene scheme is often used for CMP of the back-end of semiconductor processing to simultaneously form the trench and the via for each metal level. A thick layer of dielectric material is first formed and patterned. In a via-first implementation, vias are patterned and etched followed by trench patterning and etch. A thin diffusion barrier layer, a thin conductive seedlayer, and a thick metal layer are then deposited sequentially to fill the openings and cover the surrounding dielectric material. A first CMP process may be performed to remove the overburden of the metal over the dielectric material. Another CMP process may subsequently be performed to remove the portions of the barrier layer and the seedlayer outside the openings.
Thus, what is needed is an apparatus for and a method of delivering a slurry through a pad for chemical-mechanical polish.
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Chen George
Intel Corporation
Nguyen George
LandOfFree
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