Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-07-27
2001-11-27
Phan, Trong (Department: 2818)
Electronic digital logic circuitry
Interface
Current driving
C326S083000
Reexamination Certificate
active
06323685
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and, in particular, to an input buffer.
BACKGROUND OF THE INVENTION
Electronic systems typically are produced from component parts that are independently designed and manufactured. For example, a typical personal computer includes a microprocessor, some type of memory device such as a dynamic random access memory and a number of other integrated circuits. These components are designed according to standards for various families of integrated circuits. Integrated circuits in a “family” are designed to recognize defined voltage levels as high and low logic values used by the circuits to communicate and process data. For example,the “transistor-transistor logic” or “TTL” family of integrated circuits typically recognize 0.7 to 0.8 volts as a low logic value and 2.0 to 2.4 volts as a high logic value. In the “complimentary metal-oxide serniconductor” or “CMOS” family, circuits use a voltage that is approximately equal to the power supply as a high logic level and ground potential as the low logic level. During normal operation of the electronic systems, the components communicate with each other to share data and control signals. To do so, the components often need to recognize logic levels for a different family of integrated circuits. Designers have developed various buffer circuits that convert logic levels from a circuit in one family to logic levels of a different family.
One type of buffer circuit converts TmL logic levels for use by a CMOS circuit. The buffer typically consists of two CMOS inverters coupled in series. Unfortunately, this design draws a significant standby current. In an integrated circuit, such as a dynamic random access memory, that has a number of inputs, the standby current could decrease the overall performance of the integrated circuit. With the input buffer in active-standby mode for long periods of time, this problem is exacerbated. Other buffers include Schmitt triggers. The schmitt trigger similarly draws a significant standby current.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for buffer circuit that operates with an insignificant standby current.
SUMMARY OF THE INVENTION
The above-mentioned problems with buffer circuits and other problems are addressed by the present invention which will be understood by reading and studying the following specification. A buffer circuit is described which converts logic levels with reduced standby current.
More particularly, in one embodiment the present invention provides a buffer circuit that includes first and second inverters. The first inverter includes a first current limiter that limits the standby current used by the first inverter. Further, the second inverter is coupled to an output of the first inverter. The input buffer converts a first logic level of an input signal provided to the first inverter to a second logic level at an output of the second inverter. The buffer circuit also includes a second current limiting circuit that is coupled between the first and second inverters to further limit the standby current in the buffer circuit.
In one embodiment, the first current limiting circuit of the buffer circuit comprises a transistor that receives a feedback signal from the output of the second inverter to limit the standby current of the buffer circuit. In another embodiment, the first current limiting circuit of the buffer circuit comprises first and second transistors each having a gate coupled to receive the output signal of the second inverter such that the first transistor limits the standby current of the first inverter when the output of the buffer is a low logic level and the second transistor limits the standby current of the buffer when the output of the buffer is a high logic value.
In one embodiment, the second current limiting circuit of the buffer circuit comprises a current limiting transistor that is controlled by a reference voltage. The current limiting transistor includes a drain that is coupled to the output of the first inverter and the input of the second inverter in a standby current path for the buffer circuit. The reference voltage is coupled to the source of the current limiting transistor. The reference voltage thus establishes a low gate to source voltage for the current limiting transistor so as to limit the standby current of the buffer circuit. In another embodiment, the second current limiting circuit further comprises a voltage generator circuit that generates a reference voltage that is approximately equal to a logic level of the input signal. In another embodiment, the second current limiting circuit further comprises a pass gate transistor that is coupled between the current limiting transistor and the reference voltage. The pass gate transistor passes the reference voltage to the source of the current limiting transistor based on a feedback signal from the output of the second inverter. In another embodiment, the second current limiting circuit further comprises a circuit that delays the feedback signal when turning off the pass gate transistor to improve the stability of the output of the buffer circuit.
In another embodiment, the second current limiting circuit comprises first and second current limiting transistors. The first current limiting transistor is coupled to the output of the fist inverter to limit the standby current when a low logic level is applied to the first inverter. Further, the second current limiting transistor is coupled to the output of the first inverter to limit the standby current when a high logic level is applied to the first inverter.
In another embodiment, the present invention provides a memory device that includes a plurality of buffer circuits. The memory device is used in conjunction with an electronic system. The buffer circuits are coupled to receive input signals from the electronic system. Each buffer circuit includes first and second inverters. The inverters are coupled together so as to convert a first logic level of the input signal provided to the first inverter to a second logic level at an output of the second inverter. Each buffer circuit further includes a current limiting circuit that is coupled between the first and second inverters to limit the standby current in the buffer. The memory device further includes: a control circuit that receives control signals from the electronic system through the buffer circuits to control the operation of the memory device; an array of cells that store data for the electronic system; and an addressing circuit that receives address signals from the electronic system that identify a cell in the array of cells to be accessed by the electronic system.
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Micro)n Technology, Inc.
Phan Trong
Schwegman Lundberg Woessner & Kluth P.A.
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