Threshold voltage scalable buffer with reference level

Details Threshold voltage scalable buffer with reference level Threshold voltage scalable buffer with reference level

1996-05-15

1997-12-30

Santamauro, Jon

Electronic digital logic circuitry

Interface

Logic level shifting

326 81, 326 83, H03K 190185, H03K 190948

Patent

active

057035008

ABSTRACT:
A buffer circuit (10). The buffer circuit (10) includes a first inverter (12) with a first current limiter (18) that limits the standby current used by the first inverter (12). Further, the buffer circuit (10) includes a second inverter (14) that is coupled to an output of the first inverter (12). The input buffer (10) converts a first logic level of an input signal provided to the first inverter (12) to a second logic level at an output of the second inverter (14). The buffer circuit (10) also includes a second current limiting circuit (16) that is coupled between the first and second inverters (12 and 14) to further limit the standby current in the buffer circuit (10).

REFERENCES:
patent: 4672243 (1987-06-01), Kirsch
patent: 5150186 (1992-09-01), Pinney et al.
patent: 5304867 (1994-04-01), Morris
patent: 5406139 (1995-04-01), Sharpe-Geisler
patent: 5465234 (1995-11-01), Hannai
patent: 5594361 (1997-01-01), Campbell

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