Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
1999-12-10
2001-01-30
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
Reexamination Certificate
active
06181621
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for threshold voltage mismatch compensation in the sense transistors of a sense amplifier generally and, more particularly, to threshold voltage mismatch compensation for a first sense stage of an SRAM sense amplifier.
BACKGROUND OF THE INVENTION
An example of a dynamic random access memory voltage mismatch compensated sense amplifier can be found in IEEE JSSC, Vol. 25, No. 7, July 1993 “A High Speed, Small-Area-Threshold Voltage Mismatch Compensation Sense Amplifier for Gigabit-Scale DRAM Arrays”, which is hereby incorporated by reference in its entirety.
Such a conventional approach is suitable for Dynamic Random Access Memory (DRAM) arrays, but not as desirable for Static Random Access Memory (SRAM) arrays. Another example of a dynamic random access memory voltage mismatch compensated sense amplifier can be found in “Threshold Difference Compensated Sense Amplifier”, Shunichi Suzuki and Masaki Hirata, JSSC, Vol. SC-14, No. 6, December 1979 is also incorporated by reference in its entirety.
FIG. 1
shows a conventional uncompensated static random access memory sense amplifier circuit
10
. Such an approach has one or more of the following disadvantages: (i) no mismatch compensation; (ii) the bitline delta (i.e., differential) required for sensing is 5*94(&Dgr;Vt)=60 mV for many current SRAM designs; and/or (iii) 60 mV corresponds to a 0.5 ns to 1 ns longer access time for many SRAM designs. The following equation defines the sense voltage in the conventional circuit:
Δ
V
=
n
*
A
VTD
WL
where n=5 for memories of devices 2MEG, 4MEG, 8MEG, n is the number of standard deviations (as defined in the field of statistics) which is required to achieve a certain manufacturing yield and is related to the number of placements of the circuit in question that exist on a given chip, typically 1,000-4,000. W and L are the channel length and width of the sense devices
16
,
18
in
FIG. 1. A
VTD
is a constant established by experiment/experience.
The circuit
10
generally comprises a transistor
12
, a transistor
14
, a transistor
16
, a transistor
18
and a transistor
20
. A bitline BL may be connected to the transistor
12
. A bitline BLB may be connected to the transistor
14
. The signal STROBE may be presented to a gate at the transistor
12
, a gate at the transistor
14
and a gate at the transistor
20
. The circuit
10
illustrates an example of a conventional SRAM sense amplifier approach and has the disadvantages mentioned.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a first and a second sense transistor, a bitline and a complementary bitline, one or more first switches and one or more second switches. In one example, the first switches may be n-channel or p-channel devices. The first switches may be configured to couple the first sense transistor to the bitline and the second sense transistor to the complementary bitline. The second switches may be configured to couple the first sense transistor to the complementary bitline and the second sense transistor to the bitline. The first and second switches may be configured to provide voltage threshold matching between the first and second transistors.
The objects, features and advantages of the present invention include providing an architecture and/or method for voltage mismatch compensation that may (i) allow for an absence of a 60 mV (or more or less) bitline delta (e.g., the voltage needed to overcome a mismatch), (ii) improve the operational speed of a sense amplifier, (iii) provide a sense amplifier suitable for synchronous devices, and/or (iv) may be used for asynchronous devices which use “ATD” (Address Transition Detection) circuitry.
REFERENCES:
patent: 5828597 (1998-10-01), Madan
patent: 5831897 (1999-12-01), Hodges
patent: 5949706 (1999-09-01), Chang et al.
patent: 5991191 (1999-11-01), Rao
patent: 5999442 (1999-12-01), Van Der Sanden et al.
patent: 6005796 (1999-12-01), Sywyk et al.
Threshold Difference Compensated Sense Amplifier, by Shunichi Suzuki and Masaki Hirata, IEEE Journal of Solid-State Circuits, vol. SC-14, No. 6, Dec. 1979.
A High-Speed, Small-Area, Threshold-Voltage-Mismatch Compensation Sense Amplifier for Gigabit-Scale DRAM Arrays, by Takayuki Kawahara et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 7, Jul. 1993.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Phan Trong
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